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| 32bit TX System RISC TX19 family TMP1942CYUE TMP1942CZUE/XBG Rev1.0 March 29, 2007 TX1942CY/CZ 32-Bit RISC Microprocessor TX19 Family TMP1942CYUE/CZUE/CZXBG 1. Outline and Features The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduce code size of a 16-bit architecture. The instruction set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000ATM architecture. Additionally, the TX19 supports the MIPS16TM Application-Specific Extensions (ASE) for improved code density. The TMP1942 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1942 is suitable for low-voltage, low-power applications. Features of the TMP1942 include the following: RESTRICTIONS ON PRODUCT USE 070122EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S TMP1942CY/CZ-1 TX1942CY/CZ (1) TX19 core processor 1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed * * 2) The 16-bit ISA is object-code compatible with the code-efficient MIPS16TM ASE. The 32-bit ISA is object-code compatible with the high-performance TX39 family. Combines high performance with low power consumption. - High performance * * * * * Single clock cycle execution for most instructions 3-operand computational instructions for high instruction throughput 5-stage pipeline On-chip high-speed memory DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single clock cycle. Optimized design using a low-power cell library Programmable standby modes in which processor clocks are stopped Distinct starting locations for each interrupt service routine Automatically generated vectors for each interrupt source Automatic updates of the interrupt mask level - Low power consumption * * 3) * * * Fast interrupt response suitable for real-time control (2) Internal RAM: FDUE/FDXBG: 20KB,CYUE/CZUE/CZXBG: 16 KB Internal ROM: FDUE/FDXBG: 512KB,CYUE/CZXBG: 384KB,CYUE: 256 KB ROM correction function (8 words x 4 blocks) (For FDUE/FDXBG, only registers are available; data is not replaced.) (3) External memory expansion * * * 16-Mbyte off-chip address space for code and data External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (4) 4-channel DMA controller Interrupt- or software-triggered (5) 6 channel 8-bit PWM timer (12 channel 8-bit interval timer, 6 channel 16-bit interval timer, 6 channel 8-bit PPG output) (6) 14 channel 16-bit timer (2 channels support 2-phase input pulse counter mode.) (7) 1 channel real-time counter (RTC) (8) 5 channel general-purpose serial interface (Supports both UART and synchronous transfer modes) (9) 1 channel serial bus interface Either I2C bus mode or clock-synchronous mode can be selected. (10) 16 channel 10-bit A/D converter (with internal sample/hold) Conversion time: 2 s (throughput), 4 to 5 s (latency) (11) 3 channel 10-bit D/A converter (12) Watchdog timer (13) 4 channel chip select/wait controller TMP1942CY/CZ-2 TX1942CY/CZ (14) Interrupt sources * * * 4 CPU interrupts: software interrupt instruction 45 internal interrupts: 7 priority levels, with the exception of the watchdog timer interrupt 29 external interrupts: 7 priority levels, with the exception of the NMI interrupt The external sources include 14 KWUP sources, which are all assigned to a single interrupt vector, and 4 extended interrupts (INTB, INTC, INTD, and INTE), which are all assigned to a single interrupt vector with an identification flag. Thus, the actual number of external interrupt sources is 13. (15) 108 pin input/output ports (16) Three standby function * * * * IDLE, SLEEP, and STOP (17) Dual clocks RTC clock: Low-speed clock (32.768 kHz) (18) Clock generator On-chip PLL (x4) Clock gear: Divides the operating speed of the CPU by 1/2, 1/4 or 1/8 (19) Operating voltage range: 2.7 to 3.6 V PC and PF are 2.7 to 3.6 V or 4.5 to 5.25 V for 5 V-enabled ports. (20) Operating frequency * * * * 32 MHz (Vcc 3.0 V) 28 MHz (Vcc 2.7 V) (21) Package 144-pin QFP (16 x 16 x 1.4 (t) mm, 0.4-mm pitch): FDUE/CZUE/CYUE 177-pin CSP (13 x 13 x 1.4 (t) mm, 0.8-mm pitch): FDXBG/CZXBG Note: TMP1942FDXBG (Package: 177-pin CSP) is under development. TMP1942CY/CZ-3 TX1942CY/CZ TX19 Proccessor Core TX19 CPU (*) MROM for the mask ROM version. CZUE/XBG:384KB MAC DSU 256 KBROM (*) 16 KBRAM ROM correction DMAC (4ch) NMI INT0 (PF6) INT12 (PE67) INT34 (PA01) INT56 (PA34) INT7 (PB7) INT8A (PC02) AN07 (P5057) AN815 (P6067) ADTRG (P57) AVCC/AVSS VREFH/VREFL CG G-Bus X1 X2 XT1 (PD6) XT2 (PD7) SCOUT (P44) PLLOFF* INTC EBIF RESET* I/O Bus I/F 10-bit ADC (16ch) BW0/1 INTLV (PE7) DAOUT03 DAVCC/DAVSS DAREFH 10-bit DAC (3ch) PORT0 AD07 (P00P07) TXD0 (PD0) RXD0 (PD1) SCLK0/CTS0 (PD2) PORT1 SIO0 PORT2 AD8/A8AD15/A15 (P10P17) A0/A16A7/A23 (P20P27) TXD1 (PD3) RXD1 (PD4) SCLK1/CTS1 (PD5) RD (P30) TXD3 (PE0) RXD3 (PE1) SCLK3/CTS3 (PE2) SCK (PF3) SO/SDA (PF4) SI/SCL (PF5) TXD4 (PE3) RXD4 (PE4) SCLK4/CTS4 (PE5) TXD5 (PF0) RXD5 (PF1) SCLK5/CTS5 (PF2) TB4IN1 (PB5), TB0IN01 (PA01) TB7IN01 (P9596), TB1IN01 (PA34) TB8IN01 (PC67), TB2IN01 (PB01) TB9IN01 (PD01), TB3IN01 (PB34) TBAIN01 (PD56), TB4IN0 (PB2) TB0OUT (PA2), TB1OUT (PA5), TB2OUT (PB2), TB3OUT (PB5), TB4OUT (P92) TB5OUT (P93) TB6OUT (P94) TB7OUT (P97) WR (P31) SIO1 SIO3 PORT3 SERIAL BUS I/F HWR (P32) WAIT (P33) BUSRD (P34) BUSAK* (P35) R/W (P36) P37 SIO4 PORT4 SIO5 WDT CS0CS3 (P40P43) 16-bit TMR0-D (14ch) Real-Time Counter (RTC) INTBC (PB01) INTBCDE 8-bit TMR0/1 A/B (12ch) INTDE (PB34) TA1OUT (PA6), TA7OUT (PC5) TA3OUT (PB6), TA9OUT (PC7) TA5OUT (PC3), TABOUT (PD5) TA0IN (PA7), TA2IN (PB7), TA4IN (PC0), TA6IN (PC1) TA8IN (PC2) TAAIN (PC4) KWUP JTAG Figure 1.1 TMP1942 Block Diagram TMP1942CY/CZ-4 TX1942CY/CZ 2. Signal Descriptions This section contains pin assignments for the TMP1942 as well as brief descriptions of the functions of the TMP1942 input and output pins. 2.1 Pin Assignment Table 2.1.1 shows TMP1942 pin assignment. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Figure 2.1.1 144-Pin LQFP Pin Assignment TMP1942CY/CZ-5 TX1942CY/CZ Table 2.1.1 Pin Assignment (144-pin LQFP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VREFH VREFL P50/AN0 P51/AN1 P52/AN2 P53/AN3 DAVCC DAVSS DAREH DAOUT0 DAOUT1 DAOUT2 P54/AN4 P55/AN5 P56/AN6 P57/AN7/ADTRG P60/AN8/KEY0 DVSS P61/AN9/KEY1 P62/AN10/KEY2 P63/AN11/KEY3 P64/AN12/KEY4 P65/AN13/KEY5 P66/AN14/KEY6 P67/AN15/KEY7 DVCC3 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 DVSS P10/AD8/A8 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name P11/AD9/A9 P12/AD10/A10 P13/AD11/A11 P14/AD12/A12 P15/AD13/A13 P16/AD14/A14 P17/AD15/A15 P20/A0/A16 P21/A1/A17 P22/A2/A18 P23/A3/A19 P24/A4/A20 P25/A5/A21 P26/A6/A22 P27/A7/A23 TEST0 PLLOFF DVSS ALE DVCC3 BW1 P30/RD P31/WR P32/HWR P33/WAIT P34/BUSRQ P35/BUSAK P36/R/W P37/DSU DVSS DVCC3 P40/CS0 P41/CS1 P42/CS2 P43/CS3 P44/SCOUT Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name P90/KEY8/DCLK P91/KEY9/PCST2 P92/TB4OUT/PCST1 P93/TB5OUT/PCST0 P94/TB6OUT/SDSA0/TPC P95/TB7IN0/DBGE P96/TB7IN1/DINT P97/TB7OUT/DRESET DVCC3 PA0/TB0IN0/INT3 PA1/TB0IN1/INT4 PA2/TB0OUT PA3/TB1IN0/INT5 PA4/TB1IN1/INT6 PA5/TB1OUT PA6/TA1OUT PA7/TA0IN/KEYA DVSS RSTPUP PC0/TA4IN/INT8 PC1/TA6IN/INT9 PC2/TA8IN/INTA PC3/TA5OUT PC4/TAAIN PC5/TA7OUT PC6/TB8IN0/KEYC PC7/TB8IN1/TA9OUT DVCC52 PF0/TXD5 PF1/RXD5/KEYD PF2/SCLK5/CTS5 PF3/SCK PF4/SO/SDA PF5/SI/SCL PF6/INT0 DVCC51 Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 CVCC X2 CVSS X1 TEST1 RESET Pin Name PD6/XT1 PD7/XT2 NMI BW0 PB0/TB2IN0/INTB PB1/TB2IN1/INTC PB2/TB2OUT/TB4IN0 PB3/TB3IN0/INTD PB4/TB3IN1/INTE PB5/TB3OUT/TB4IN1 PB6/TA3OUT DVSS DVCC3 PB7/TA2IN/INT7/KEYB PD0/TXD0/TB9IN0 PD1/RXD0/TB9IN1 PD2/SCLK0/CTS0 PD3/TXD1/TBAIN0 PD4/RXD1/TBAIN1 PD5/SCLK1/CTS1/TABOUT PE0/TXD3 PE1/RXD3 PE2/SCLK3/CTS3 PE3/TXD4 PE4/RXD4 PE5/SCLK4/CTS4 PE6/INT1/BOOT PE7/INT2/INTLV AVCC AVSS TMP1942CY/CZ-6 TX1942CY/CZ Figure 2.1.2 shows pin assignment for the 177-pin model of the TMP1942. A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 M5 N5 P5 R5 M6 N6 P6 R6 M7 N7 P7 R7 M8 N8 P8 R8 M9 N9 P9 R9 M10 N10 P10 R10 M11 N11 P11 R11 A5 B5 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 B8 C8 D8 A9 B9 C9 D9 A10 B10 C10 D10 A11 B11 C11 D11 A12 B12 C12 D12 E12 F12 G12 H12 J12 K12 L12 M12 N12 P12 R12 A13 B13 C13 D13 E13 F13 G13 H13 J13 K13 L13 M13 N13 P13 R13 A14 B14 C14 D14 E14 F14 G14 H14 J14 K14 L14 M14 N14 P14 R14 A15 B15 C15 D15 E15 F15 G15 H15 J15 K15 L15 M15 N15 P15 R15 Figure 2.1.2 177-Pin CSP Pin Assignment TMP1942CY/CZ-7 TX1942CY/CZ Table 2.1.2 Pin Assignment (177-pin CSP) Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 VREFL AVSS AVCC PE7/INT2/INTLV PE3/TXD4 TCK (JTAG) PD2/SCLK0/CTS0 PB5/TB3OUT/TB4IN1 PB1/TB2IN1/INTC PD7/TX2 PD6/TX1 X1 X2 CVCC NC NC NC PE6/INT1 PE4/RXD4 TRST (JTAG) PD5/SCLK1/CTS1/TABOUT PD0/TXD0/TB9IN0 DVCC3 PB4/TB3IN1/INTE PB0/TB2IN0/INTB NC RESET CVSS DVCC51 NC VREFH NC PE5/SCLK4/CTS4 PE2/SCLK3/CTS3 PE1/RXD3 PD4/RXD1/TBAIN1 PD1/RXD0/TB9IN1 PB6/TA3OUT PB3/TB3IN0/INTD BW0 NC TEST1 PF4/SO/SDA PF5/SI/SCL NC Pin Name Pin No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E5 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 H12 Pin Name P50/AN0 DAVSS P52/AN2 P51/AN1 PE0/TXD3 PD3/TXD1/TBAIN0 PB7/TA2IN/INT7/KEYB DVSS PB2/TB2OUT/TB4IN0 NMI NC NC PF1/RXD5/KEYD PF3/SCK PF6/INT0 DAVCC DAOUT0 DAREFH P53/AN3 NC (Bonding not applied) Pin No. H13 H14 H15 J1 J2 J3 J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 NC NC Pin Name Pin No. N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Pin Name P16/AD14/A14 P21/A1/A17 P25/A5/A21 DVSS TEST0 P30/RD P32/HWR P37 DVSS P41/CS1 P91/KEY9 NC NC P10/AD8/A8 P12/AD10/A10 P20/A0/A16 P22/A2/A18 P26/A6/A22 TDO (JTAG) ALE BW1 P33/WAIT TDI (JTAG) P40/CS0 P42/CS2 P44/SCOUT NC P11/AD9/A9 NC NC P13/AD11/A11 P17/AD15/A15 P23/A3/A19 P27/A7/A23 NC P31/WR P35/BUSAK DVCC3 NC P43/CS3 NC P90/KEY8 DVSS P67/AN15/KEY7 P65/AN13/KEY5 P66/AN14/KEY6 P64/AN12/KEY4 PA6/TA1OUT PA7/TA0IN/KEYA NC PA5/TB1OUT P01/AD1 DVCC3 NC NC PA2/TB0OUT PA3/TB1IN0/INT5 PA4/TB1IN1/INT6 PA1/TB0IN1/INT4 P04/AD4 P02/AD2 TMS (JTAG) P00/AD0 P97/TB7OUT DVCC3 PA0/TB0IN0/INT3 P96/TB7IN1 P07/AD7 P05/AD5 P03/AD3 P14/AD12/A12 P15/AD13/A13 P24/A4/A20 PLLOFF NC DVCC3 P34/BUSRQ P36/R/W P93/TB5OUT P94/TB6OUT P95/TB7IN0 P92/TB4OUT NC DVSS P06/AD6 PC6/TB8IN0/KEYC DVCC52 PF0/TXD5 PF2/SCLK5/CTS5 DAOUT1 P55/AN5 P54/AN4 DAOUT2 PC2/TA8IN/INTA PC4/TAAIN PC5/TA7OUT PC7/TB8IN1/TA9OUT P56/AN6 P61/AN9/KEY1 NC P60/AN8/KEY0 PC0/TA4IN/INT8 PC1/TA6IN/INT9 NC PC3/TA5OUT DVSS P63/AN11/KEY3 P57/AN7/ADTRG P62/AN10/KEY2 RSTPUP TMP1942CY/CZ-8 TX1942CY/CZ 2.2 Pin Usage Information Table 2.2.1 lists the names and functions of the TMP1942's input/output pins. Table 2.2.1 Pin Names and Functions Pin Name # of Pins P00~P07 AD0~AD7 P10~P17 AD8~AD15 A8~A15 P20~P27 A0~A7 A16~A23 P30 RD P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK P36 R/W P37 DSU 1 1 1 1 1 1 1 1 8 8 8 Type Input/output Input/output Input/output Input/output Output Input/output Output Output Output Output Output Output Input/output Output Input/output Input Input/output Input Input/output Output Input/output Output Input/output Input Function Port 0: Individually programmable as input or output Address (Lower): Bits 0-7 of the address/data bus Port 1: Individually programmable as input or output Address/Data (Upper): Bits 8-15 of the address/data bus Address: Bits 8-15 of the address bus Port 2: Individually programmable as input or output Address: Bits 0-7 of the address bus Address: Bits 16-23 of the address bus Port 30: Output-only Read Strobe: Asserted during a read operation from an external memory device Port 31: Output-only Write Strobe: Asserted during a write operation on D0-D7 Port 32: Programmable as input or output (with internal pull-up resister) Higher Write Strobe: Asserted during a write operation on D8-D15 Port 33: Programmable as input or output (with internal pull-up resister) Wait: Causes the CPU to suspend external bus activity Port 34: Programmable as input or output (with internal pull-up resister) Bus Request: Asserted by an external bus master to request bus mastership Port 35: Programmable as input or output (with internal pull-up resister) Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to BUSRQ . Port 36: Programmable as input or output (with internal pull-up resister) Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy cycle, 0 = write cycle Port 37: Programmable as input or output (with internal pull-up resister) This pin is used to select the operating mode during reset. The TMP1940CYAF enters NORMAL mode when this pin is sampled high at the rising edge of RESET . This pin should not be pulled down to a logic 0 during a reset sequence. The TMP1940FDBF, which has an on-chip flash, uses this pin as an interface to the DSU tool. For details, refer to Part 4, TMP1940FDBF. Port 40: Programmable as input or output (with internal pull-up resister) Chip Select 0: Asserted low to enable external devices at programmed addresses Port 41: Programmable as input or output (with internal pull-up resister) Chip Select 1: Asserted low to enable external devices at programmed addresses Port 42: Programmable as input or output (with internal pull-up resister) Chip Select 2: Asserted low to enable external devices at programmed addresses Port 43: Programmable as input or output (with internal pull-up resister) Chip Select 3: Asserted low to enable external devices at programmed addresses Port 44: Programmable as input or output System Clock Output: Drives out a clock signal at the same frequency as the CPU clock (high-speed or low-speed) Port 5: Input-only Analog input: Input to the A/D converter External start request for the A/D converter (multiplexed with P57) Port 6: Input-only Analog input: Input to the A/D converter Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port 90: Programmable as input or output DSU pin Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) P40 CS0 P41 CS1 P42 CS2 P43 CS3 P44 SCOUT P50~P57 AN0~AN7 ADTRG P60~P67 AN8~AN15 KEY0-KEY7 P90 DSU (DCLK) KEY8 1 1 1 1 1 Input/output Output Input/output Output Input/output Output Input/output Output Input/output Output 8 Input Input Input 1 Input/output Input Output 1 Input/output Output Input TMP1942CY/CZ-9 TX1942CY/CZ Pin Name # of Pins P91 DSU (PCST2) KEY9 P92 DSU (PCST1) TB40UT P93 DSU (PCST0) TB5OUT P94 DSU (SDSA0/TPC) TB6OUT P95 DSU (DBGE*) TB7IN0 P96 DSU (DINT*) TB7IN1 P97 DSU (DRESET) TB7OUT PA0 TB0IN0 INT3 PA1 TB0IN1 INT4 PA2 TB0OUT PA3 TB1IN0 INT5 PA4 TB1IN1 INT6 PA5 TB1OUT PA6 TA1OUT PA7 TA0IN KEYA PB0 TB2IN0 INTB 1 1 1 1 1 1 1 1 1 Output Input/output Input Input Input/output Input Input Input/output Output Input/output Input Input Input/output Input Input Input/output Output Input/output Output Input/output Input Input Input/output Input Input 16-Bit Timer 7 Output: Output from 16-bit Timer 7 Port A0: Programmable as input or output 16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit Timer 0 Interrupt Request 3: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive 1 Input/output Input 1 Input/output Input 1 Output Input/output Input 16-Bit Timer 6 Output: Output from 16-bit Timer 6 Port 95: Programmable as input or output DSU pin 16-Bit Timer 7 Input 0: Count/capture trigger input to 16-bit Timer 7 Port 96: Programmable as input or output DSU pin 16-Bit Timer 7 Input 1: Capture trigger input to 16-bit Timer 7 Port 97: Programmable as input or output DSU pin 1 1 1 1 Type Input/output Output Input Input/output Output Output Input/output Output Output Input/output Output DSU pin Function Port 91: Programmable as input or output Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port 92: Programmable as input or output DSU pin 16-Bit Timer 4 Output: Output from 16-bit Timer 4 Port 93: Programmable as input or output DSU pin 16-Bit Timer 5 Output: Output from 16-bit Timer 5 Port 94: Programmable as input or output DSU pin Port A1: Programmable as input or output 16-Bit Timer 0 Input 1: Capture trigger input to 16-bit Timer 0 Interrupt Request 4: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port A2: Programmable as input or output 16-Bit Timer 0 Output: Output from 16-bit Timer 0 Port A3: Programmable as input or output 16-Bit Timer 1 Input 0: Count/capture trigger input to 16-bit Timer 1 Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port A4: Programmable as input or output 16-Bit Timer 1 Input 1: Capture trigger input to 16-bit Timer 1 Interrupt Request 6: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port A5: Programmable as input or output 16-Bit Timer 1 Output: Output from 16-bit Timer 1 Port A6: Programmable as input or output 8-Bit Timer 0/1 Output: Output from 8-bit Timer 0 or 1 Port A7: Programmable as input or output 8-Bit Timer 0 Input: Input to 8-bit Timer 0 Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port B0: Programmable as input or output 16-Bit Timer 2 Input 0: Count/capture trigger input/2-phase input pulse counter input to 16-bit Timer 2 Interrupt Request B: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive TMP1942CY/CZ-10 TX1942CY/CZ Pin Name # of Pins PB1 TB2IN1 INTC 1 Type Input/output Input Input Function Port B1: Programmable as input or output 16-Bit Timer 2 Input 1: Capture trigger input/2-phase input pulse counter input to 16-bit Timer 2 Interrupt Request C: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive PB2 TB2OUT TB4IN0 PB3 TB3IN0 INTD 1 Input/output Output Input Port B2: Programmable as input or output 16-Bit Timer 2 Output: Output from 16-bit Timer 2 16-Bit Timer 4 Input 0: Count/capture trigger input to 16-bit Timer 4 Port B3: Programmable as input or output 16-Bit Timer 3 Input 0: Count/capture trigger input/2-phase input pulse counter input to 16-bit Timer 3 Interrupt Request D: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive 1 Input/output Input Input PB4 TB3IN1 INTE 1 Input/output Input Input Port B4: Programmable as input or output 16-Bit Timer 3 Input 1: Capture trigger input/2-phase input pulse counter input to 16-bit Timer 3 Interrupt Request E: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive PB5 TB3OUT TB4IN1 PB6 TA3OUT PB7 TA2IN INT7 KEYB PC0 TA4IN INT8 PC1 TA6IN INT9 PC2 TA8IN INTA PC3 TA5OUT PC4 TAAIN PC5 TA7OUT PC6 TB8IN0 KEYC PC7 TB8IN1 TA9OUT PD0 TXD0 TB9IN0 1 Input/output Output Input Port B5: Programmable as input or output 16-Bit Timer 3 Output: Output from 16-bit Timer 3 16-Bit Timer 4 Input 1: Capture trigger input to 16-bit Timer 4 Port B6: Programmable as input or output 8-Bit Timer 2/3 Output: Output from 8-bit Timer 2 or 3 Port B7: Programmable as input or output 8-Bit Timer 2 Input: Input to 8-bit Timer 2 Interrupt Request 7: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port C0: Programmable as input or output 8-Bit Timer 4 Input: Input to 8-bit Timer 4 Interrupt Request 8: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port C1: Programmable as input or output 8-Bit Timer 6 Input: Input to 8-bit Timer 6 Interrupt Request 9: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port C2: Programmable as input or output 8-Bit Timer 8 Input: Input to 8-bit Timer 8 Interrupt Request A: Programmable to be high-level, low-level, rising-edge or falling-edge sensitive Port C3: Programmable as input or output 8-Bit Timer 4/5 Output: Output from 8-bit Timer 4 or 5 Port C4: Programmable as input or output 8-Bit Timer A Input: Input to 8-bit Timer A Port C5: Programmable as input or output 8-Bit Timer 6/7 Output: Output from 8-bit Timer 6 or 7 Port C6: Programmable as input or output 16-Bit Timer 8 Input 0: Count/capture trigger input to 16-bit Timer 8 Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port C7: Programmable as input or output 16-Bit Timer 8 Input 1: Capture trigger input to 16-bit Timer 8 8-Bit Timer 8/9 Output: Output from 8-bit Timer 8 or 9 Port D0: Programmable as input or output Serial Transmit Data 0 Programmable as an open-drain output 16-Bit Timer 9 Input 0: Count/capture trigger input to 16-bit Timer 9 1 1 Input/output Output Input/output Input Input Input 1 Input/output Input Input 1 Input/output Input Input 1 Input/output Input Input 1 1 1 1 Input/output Output Input/output Input Input/output Output Input/output Input Input 1 Input/output Input Output 1 Input/output Output Input TMP1942CY/CZ-11 TX1942CY/CZ Pin Name # of Pins PD1 RXD0 TB9IN1 PD2 SCLK0 CTS0* PD3 TXD1 TBAIN0 PD4 RXD1 TBAIN1 PD5 SCLK1 CTS1 TABOUT PD6 XT1 PD7 XT2 PE0 TXD3 PE1 RXD3 PE2 CTS3* 1 1 1 1 1 1 1 1 1 1 Type Input/output Input Input Input/output Input/output Input Input/output Output Input Input/output Input Input Input/output Input/output Input Output Input/output Input Input/output Output Input/output Output Input/output Input Input/output Input/output Input Serial Receive Data 0 Function Port D1: Programmable as input or output 16-Bit Timer 9 Input 1: Capture trigger input to 16-bit Timer 9 Port D2: Programmable as input or output Serial Clock Input/Output 0 Serial Clear-to-Send 0 Programmable as an open-drain output Port D3: Programmable as input or output Serial Transmit Data 1 Programmable as an open-drain output 16-Bit Timer A Input 0: Count/capture trigger input to 16-bit Timer A Port D4: Programmable as input or output Serial Receive Data 1 16-Bit Timer A Input 1: Capture trigger input to 16-bit Timer A Port D5: Programmable as input or output Serial Clock Input/Output 1 Serial Clear-to-Send 1 Programmable as an open-drain output 8-Bit Timer A/B Output: Output from 8-bit Timer A or B Port D6: Programmable as input or open-drain output Connection pin for a low-speed crystal Port D7: Programmable as input or open-drain output Connection pin for a low-speed crystal Port E0: Programmable as input or output Serial Transmit Data 3 Programmable as an open-drain output Port E1: Programmable as input or output Serial Receive Data 3 Port E2: Programmable as input or output Serial Clock Input/Output 3 Serial Clear-to-Send 3 Programmable as an open-drain output Port E3: Programmable as input or output Serial Transmit Data 4 Programmable as an open-drain output Port E4: Programmable as input or output Serial Receive Data 4 Port E5: Programmable as input or output Serial Clock Input/Output 4 Serial Clear-to-Send 4 Programmable as an open-drain output Port E6: Programmable as input or output Interrupt request 1: Individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. PE3 TXD4 PE4 RXD4 PE5 SCLK4 CTS4 PE6 INT1 BOOT 1 Input/output Output 1 1 Input/output Input Input/output Input/output Input 1 Input/output Input Single-boot mode setting pin: Used when rewriting built-in flash memory (low active). During normal operation, this pin should be pulled up. This pin should always be pulled up for the mask ROM version. PE7 INT2 INTLV 1 Input/output Input Port E7: Programmable as input or output Interrupt request 2: Individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. Interleave mode setting pin: This pin should be pulled up when using interleave mode. Otherwise, it should be pulled down. PF0 TXD5 1 Input/output Output Port F0: Programmable as input or output Serial Transmit Data 5 Programmable as an open-drain output TMP1942CY/CZ-12 TX1942CY/CZ Pin Name # of Pins PF1 RXD5 KEYD PF2 SCLK5 CTS5 PF3 SCK PF4 SO SDA PF5 SI SCL PF6 INT0 ALE TEST0 TEST1 RSTPUP DAOUT0-2 NMI BW0~1 PLLOFF RESET VREFH VREFL AVCC AVSS DAVCC DAVSS DAREFH X1/X2 CVCC CVSS DVCC3 DVCC51 DVCC52 DVSS 1 1 1 1 3 1 2 1 1 1 1 1 1 1 1 1 2 1 1 4 1 1 5 1 1 1 1 1 Type Input/output Input Input Input/output Input/output Input Input/output Input/output Input/output Output Input/output Input/output Input Input/output Input/output Input Output Input Input Input Output Input Input Input Input Input Input Input/output Serial Receive Data 5 Function Port F1: Programmable as input or output Key on wake-up input (with internal pull-up resister) (dynamic pull-up selectable) Port F2: Programmable as input or output Serial Clock Input/Output 5 Serial Clear-to-Send 5 Programmable as an open-drain output Port F3: Programmable as input or output Clock input/output pin when the serial bus interface is in SIO mode Port F4: Programmable as input or output Data transmission pin when the serial bus interface is in SIO mode Data transmission/reception pin when the serial bus interface is in I C mode Programmable as an open-drain output Port F5: Programmable as input or output Data reception pin when the serial bus interface is in SIO mode Clock input/output pin when the serial bus interface is in I C mode Programmable as an open-drain output Port F6: Programmable as input or output Interrupt request 0: Individually programmable to be high-level, low-level, rising-edge or falling-edge sensitive. Address Latch Enable (This signal is driven out only when external memory is accessed) Test pin Test pin When this pin is driven high (upon reset), pull-up for ports 3 and 4 is enabled. When this pin is driven low, pull-up is disabled. D/A converter output Non-maskable Interrupt Request: Causes an NMI interrupt on the falling edge Set both AM0 and AM1 to 1. This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is used; otherwise, it should be tied to logic 0. Reset (with internal pull-up resister): Initializes the whole TMP1940CYAF Input pin for high reference voltage for the A/D converter. Input pin for low reference voltage for the A/D converter. Power supply pin for the A/D converter. This pin should always be connected to power supply even when the A/D converter is not used. Ground pin for the A/D converter. This pin should always be connected to ground even when the A/D converter is not used. Power supply pin for the D/A converter. This pin should always be connected to power supply even when the D/A converter is not used. Ground pin for the D/A converter. This pin should always be connected to ground even when the D/A converter is not used. Reference voltage input pin for the D/A converter Resonator connecting pin Power supply pin for the oscillator Ground pin for the oscillator (0 V) Power supply pins Power supply pin (port F) Power supply pin (port C) Ground pins (0 V) 2 2 Port C becomes a 5 V port when a 5 V power supply is connected to DVCC52. Port F becomes a 5 V port when a 5 V power supply is connected to DVCC51. Note: When the DSU is enabled, port 9 functions as the processor probe interfacing signal regardless of the setting of the port 9 control register (P9CR). TMP1942CY/CZ-13 TX1942CY/CZ The following table lists the JTAG specific pins added to the CSP package: Pin Name # of Pins TRST TCK TDI TDO TMS 1 1 1 1 1 Type Input Input Input Output Input Function JTAG reset pin (with internal pull-up resistor) JTAG clock pin (with internal pull-up resistor) JTAG data input pin (with internal pull-up resistor) JTAG data output pin JTAG mode switching input pin (with internal pull-up resistor) TMP1942CY/CZ-14 TMP1942CY/CZ 3. Functional Description This section describes the functions and basic operation of each individual circuit block in the TMP1942 series devices. 3.1 Processor Core The TX1942 contains a high-performance 32-bit processor core (the TX19 processor core). For details of the operation of the processor core, refer to "TX19 Family Architecture". Functions unique to the TMP1942, which are not explained in "TX19 Family Architecture", are described below. Recommended power-on sequence: In powering up this device, it is recommended that the DVCC3 be turned on first. At power-on, the pull-up resistors and input & output buffers pull-down resistors attached to the I/O ports of the 5V supply domain may rail become unstable or a through current may pass through the port until the DVCC3 has stabilized, when an injection order is not kept. 3.1.1 Reset Operation To reset the TMP1942, RESET must be input Low (at 0) for at least 12 system clock cycles while the power supply voltage is within the rated operating range and the internal high-frequency oscillator is oscillating stably. (With the device operating at 32 MHz, this period is equal to 3 s if the PLL is being used and 6 s if the PLL is not being used.) After a reset the PLL-multiplied clock is specified by the setting of the PLLOFF pin and the clock gear is initialized to 1/8 mode. To reset the TMP1942, RESET must be asserted for at least 12 system clock periods after the power supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 3 s at 32 MHz when the on-chip PLL is utilized, and 6s otherwise. After a reset, either the PLL-multiplied clock or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected clock is geared down to 1/8 for internal operation. The following occurs as a result of a reset: * * The System control coprocessor (CP0) registers within the TX19 core processor are initialized. For details, refer to the Architecture manual. The Reset exception is taken. Program control is transferred to the exception handler at a predefined address. This predefined location is called an exception vector, which directly indicates the start of the actual exception handler routine. The Reset exception is always vectored to virtual address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception). All on-chip I/O peripheral registers are initialized. All port pins, including those multiplexed with on-chip peripheral functions, are configured as either general-purpose inputs or general-purpose outputs. * * TMP1942CY/CZ-15 TMP1942CY/CZ 3.2 Memory Map Figure 3.2.1 shows a memory map of the TMP1942. Virtual address 0xFFFF_FFFF 16 Mbytes reserved 0xFF00_0000 Kseg2 (cacheable) 0xC000_0000 0xBFC0_0000 Kseg1 (uncacheable) 0xA000_0000 Kseg0 (cacheable) 0x8000_0000 16 Mbytes reserved Physical address 16 Mbytes reserved Kseg2 (1 Gbyte) 16 Mbytes reserved Internal I/O (Reserved) Internal RAM (16KB) 0xFFFF_E000 0xFFFF_AFFF 0xFFFF_7000 (Reserved) Reserved for debugging (2 MB) 0xFF3F_FFFF 0xFF20_0000 (Reserved) 0xFF00_0000 Kuseg (2Gbyte) Internal ROM area reflected Kuseg (cacheable) Cannot be accessed Internal ROM 0x0007_FFFF 0x0000_0000 512 Mbytes 0x4003_FFFF 0x4000_0000 0x1FC3_FFFF 0x1FC0_0000 User program area 0x1FC3_FFFF 0x1FC0_0400 Maskable interrupt area Exception vector area 0x1FC0_0000 Figure 3.2.1 Memory Map Note 1: The internal ROM is mapped into the memory space from 0x1FC0_0000 to 0x1FC3_FFFF (for a 256-KB ROM) or 0x1FC0_0000 to 0x1FC5_FFFF (for a 384-KB ROM). The internal RAM is mapped into the memory space from 0xFFFF_8000 to 0xFFFF_BFFF (for a 16-KB RAM). Note 2: The memory space from 0xFFFF_4000 to 0xFFFF_BFFF is a reserved RAM area. Any area other than those shown above, where physical memory is located, should not be accessed. Note 3: The internal memory data is stored in contiguous physical address locations starting at 0x1FC0_0000. If exception vector addresses are placed in internal ROM, the system control coprocessor (CP0) Status register's BEV bit must be set to 1 (the default). (This is because exception vector addresses are dispersed if BEV = 0.) If memory is added externally, the BEV bit can be set to 0. However, since a virtual address space of 0x0000_0000 32 KB is easier to access for reasons of code efficiency, this area is reflected in the contiguous physical address space from 0x4000_0000 upwards (as indicated by the shaded area) which corresponds to a virtual address space starting at 0x0000_0000 and which is equal in size to the internal memory. Hence, accessing this area is equivalent to accessing the internal memory. Example: Using 32-bit ISA * Access to the 0x0000_0000 32 KB area ADDIU SW r2, r0, 7 ; r 2 (0x0000_0007) r2, Io (_t) (r0) ; 0x0000_xxxx (r2) Can be accessed using a single instruction. * Access to areas other than 0x0000_0000 32 KB LUI ADDIU SW Note 4: r3, hi (_f) r2, r0, 8 ; Upper address is set to r3. ; r2 (0x0000_0008) r2, Io (_f) (r3) ; Memory is accessed after lower address has been set. The TX1942 supports access to only 16 Mbytes of physical space as external address space. A 16-Mbyte physical address space can be placed in any chip-select area within the CPU's 3.5 Gbytes of physical address space. However, when access to the internal memory, internal I/O space or a reserved area is performed, the external address space cannot be accessed simultaneously, since the other types of access have priority. Note 5: Do not place an instruction in the last four words of the physical area. * The relevant area of the internal ROM is 0x1FC3_FFF0 to 0x1FC3_FFFF (for a 256-KB ROM) or 0x1FC5_FFF0 to 0x1FC5_FFFF (for a 384-KB ROM). * If ROM is added externally, this restriction applies to the last four words of the installed memory (system-dependent). TMP1942CY/CZ-16 TMP1942CY/CZ 3.3 Clock/Standby Control There are essentially two modes of clock operation: single-clock mode (which uses only the X1 and X2 pins) and dual-clock mode (which uses the X1 and X2 pins as well as the XT1 and XT2 pins). Figure 3.3.1 shows the state transition diagram for each operation mode. Reset Reset terminated IDLE mode (CPU halted) (I/O select operation) Instruction Interrupt NORMAL mode (fc/gear value) Instruction Interrupt STOP mode (all circuits turned off) (a) State transition in single-clock mode Reset Reset terminated IDLE mode (CPU halted) (I/O select operation) Instruction Interrupt Instruction Interrupt SLEEP mode (fc only) (only real-time clock timer operating) Instruction Interrupt NORMAL mode (fc/gear value) Instruction Instruction Interrupt Instruction Interrupt STOP mode (all circuits turned off) SLOW mode (fs) Note 1: Note 2: Note 3: Before transition to SLOW/SLEEP mode can occur, the low-speed oscillator (fs) must be oscillating stably. When SLEEP mode is terminated, the device returns to the state in which it was placed before entering SLEEP mode. The state to which the device returns when STOP mode is terminated can be specified using system control register SYSCR0. (b) State transition in dual-clock mode Figure 3.3.1 State Transition Diagrams for Different Modes Reset Reset terminated PLLOFF pin (High) PLL clock used NORMAL mode fc = fpll = fosc x 4 fsys = fc/8 fsys = fosc/2 fperiph = fsys Reset Reset terminated PLLOFF pin (Low) PLL not used NORMAL mode fc = fosc/2 fsys = fc/8 fsys = fosc/16 fperiph = fsys A. When a clock generated by the PLL is used B. When the PLL is not used Figure 3.3.32 Default States When the PLL is Used and Those When the PLL is Not Used fosc: fs: fpll: fc: fgear: fperiph: Clock frequency input via X1 and X2 pins Clock frequency input via XT1 and XT2 pins Clock frequency multiplied (x4) by PLL Clock frequency selected by setting of PLLOFF pin Clock frequency selected by SYSCR1 System clock fsys: Clock frequency selected by SYSCR1 TMP1942CY/CZ-17 TMP1942CY/CZ 3.3.1 Block Diagram of Clock Circuits 1. Main system clock * * * * A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock. PLLOFF The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin. When the PLL is enabled, the input clock frequency is multiplied by four. The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.) Input clock frequency Input Frequency Range fmax 32 MHz 20 MHz 20 MHz 16 MHz *1 fmin 2.5 MHz 1 MHz 1 MHz 1.25 MHz PLLON (for both resonator and external input) Resonator PLLOFF External input 5~8 (MHz) 16~20 (MHz) 16~20 (MHz) 2032 (MHz) *1. SYSCR1 2. Sub-system clock * * * Generated using a 32.768-kHz resonator (external input also accepted). SLOW mode: The CPU runs at low speed. SLEEP mode: Only the timer for real-time clock, 2-phase pulse input counter, and dynamic pull-up operate. TMP1942CY/CZ-18 TMP1942CY/CZ 3. Block diagram SYSCR0 SYSCR0 Warm-up timer Lock-up (PLL) timer fgear fc fperiph (to peripheral I/O) fs Fpll = fosch x 4 Selector PLL /2 /2 /4 /8 fsys SYSCR1 High-speed oscillator fosc PLLOFF (default pin setting) SYSCR1 ROM RAM Peripheral I/O (prescaler input) TMRA/B, SIO SBI, ADC DMAC INTC /2 fperiph /2 /4 Peripheral I/O ADC,DA,TMRA/B, SIO,SBI,PIO, WDT, RTC fs Timer for real-time clock 2-phase pulse input counter KWUP SYSCR3 Note 1: When using the clock gear to reduce the system clock frequency, make sure that Tn of the prescaler output for each peripheral I/O block satisfies the following relationship: Tn TMP1942CY/CZ 3.3.2 Clock Generator (CG) Registers (1) Clock-related registers 7 SYSCR0 Bit Symbol After reset Function XEN 1 (0xFFFF_EE00) Read/Write 0 1 0 Low-speed oscillator after exit from STOP mode High-speed Low-speed High-speed oscillator oscillator oscillator after exit from STOP mode 6 XTEN 5 RXEN 4 RXTEN R/W 3 RSYSCK 0 Clock selection after exit from STOP mode 2 WUEF 0 1 PRCK1 0 0 PRCK0 0 Oscillator Prescaler clock selection warm-up timer (WUP) 00: fperiph/4 control 01: fperiph/2 Write 0: 10: fperiph Don't care 11: (reserved) Write 1: 0: Turned off 0: Turned off 0: Turned off 0: Turned off 0: High speed WUP start 1: Oscillating 1: Oscillating 1: Oscillating 1: Oscillating 1: Low speed Read 0: WUP finished Read 1: WUP operating 15 SYSCR1 Bit Symbol After reset Function (0xFFFF_EE01) Read/Write 14 13 SYSCK R/W 12 FPSEL 0 fperiph selection 11 DFOSC 0 High-speed oscillator frequency division selection 0: Divide by 2 1: Divide by 1 10 9 GEAR1 R/W 8 GEAR0 1 - 0 System clock selection - 1 High-speed clock (fc) gear selection 0: High speed 0: fgear (fc) 1: fc 1: Low speed (fs) 00: fc 01: fc/2 10: fc/4 11: fc/8 23 SYSCR2 Bit Symbol After reset Function (0xFFFF_EE02) Read/Write 0 High-speed oscillator driving capability control 0: Normal 1: Weak 22 21 WUPT1 R/W 1 20 WUPT0 0 19 STBY1 1 18 STBY0 17 - 16 DRVE R/W 0 1: Pins are also driven in STOP mode. DRVOSCH DRVOSCL 0 1 - Low-speed Oscillator warm-up time oscillator selection driving capability 2 control 00: 2 /input frequency 8 01: 2 /input frequency 14 0: Normal 10: 2 /input frequency 16 11: 2 /input frequency 1: Weak Standby mode selection 00: Reserved 01: STOP mode 10: SLEEP mode 11: IDLE mode 31 SYSCR3 Bit Symbol After reset Function (0xFFFF_EE03) Read/Write 30 SCOSEL R/W 0 SCOUT output selection 0: fs 1: fsys 29 - 28 ALESEL R/W 1 ALE output width selection 0: fsys x 0.5 1: fsys x 1.5 27 - 26 - 25 LUPFG R 0 24 LUPTM R/W 0 selection Lock-up flag Lock-up time 0: LUP finished 1: LUP in operation 0: 216/input frequency 1: 212/input frequency TMP1942CY/CZ-20 TMP1942CY/CZ Note 1: Standby mode selection depends on the settings of the Doze and Halt bits in the CP0's internal Config register. If the Halt bit = 1, the device will enter the mode selected by STBY[1:0]. If the Doze bit = 1, the device will always enter IDLE mode. Note 2: When the PLL is not used, set the LUPTM bit in the SYSCR3 register to 1 (i.e., select 212/input frequency). Note3: The WURT1-WUPT0 bitys in the SYSCR2 must be not be changed during the oscillator warm-up event ( e.g. SLEEP-NORMAL-SLEEP) Note 4: Do as follows to change the operating mode immediately after the device has warmed up from the clock stop state (e.g., from SLEEP mode to NORMAL mode to SLEEP mode). * Warming up by hardware (1) Moving from STOP or SLEEP mode to NORMAL mode 1) When the PLL is used Before moving to the next operating mode, ensure that the lock-up bit, LUPFG, in the SYSCR3 register has been cleared to zero and wait for five or more instructions to complete (including the instruction to check the LUPFG flag). 2) When the PLL is not used * When the oscillator warm-up time (SYSCR2 * When the oscillator warm-up time (SYSCR2 (2) Moving from NORMAL mode to SLOW mode Before moving to SLOW mode, ensure that the warm-up end flag (i.e., the WUEF bit in the SYSCR0 register) is cleared and wait for five or more instructions to complete. TMP1942CY/CZ-21 TMP1942CY/CZ (2) Standby (STOP/SLEEP mode) termination interrupts 7 Bit Symbol IMCGA0 (0xFFFF_EE10) Read/Write After reset Function 6 5 EMCG01 1 R/W 4 EMCG00 3 2 1 0 INT0EN R/W 0 INT0 request input 0: Disable 1: Enable 0 Active state setting for INT0 standby termination request 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 Bit Symbol Read/Write After reset Function 14 13 EMCG11 1 R/W 12 EMCG10 0 11 DFOSC 10 9 8 INT1EN R/W 0 INT1 request input 0: Disable 1: Enable Active state setting for INT1 standby termination request 00: Low level 01: High level 10: Falling edge 11: Rising edge 23 Bit Symbol Read/Write After reset Function 22 21 EMCG21 1 R/W 20 EMCG20 19 18 17 16 INT2EN R/W 0 INT2 request input 0: Disable 1: Enable 0 Active state setting for INT2 standby termination request 00: Low level 01: High level 10: Falling edge 11: Rising edge 31 Bit Symbol Read/Write After reset Function 30 29 EMCG31 1 R/W 28 EMCG30 27 26 25 24 INT3EN R/W 0 INT3 request input 0: Disable 1: Enable 0 Active state setting for INT3 standby termination request 00: Low level 01: High level 10: Falling edge 11: Rising edge TMP1942CY/CZ-22 TMP1942CY/CZ 7 IMCGB0 Bit Symbol (0xFFFF_EE14) Read/Write After reset Function 6 5 EMCG41 1 R/W 4 EMCG40 3 2 1 0 INT4EN R/W 0 INT4 request input 0: Disable 1: Enable 0 Active state setting for INT4 standby termination request 00: Low level 01: High level 10: Falling edge 11: Rising edge 15 Bit Symbol Read/Write After reset Function 14 13 EMCG51 1 R/W 12 EMCG50 11 10 9 8 KWUPEN R/W 0 KWUP request input 0: Disable 1: Enable 0 These bits should always be set to 01. 23 Bit Symbol Read/Write After reset Function 22 21 EMCG61 1 R/W 20 EMCG60 19 18 17 16 INTBCDEEN R/W 0 INTBCDE request input 0: Disable 1: Enable 0 These bits should always be set to 01. 31 Bit Symbol Read/Write After reset Function 30 29 EMCG71 1 R/W 28 EMCG70 27 26 25 24 INTRTCEN R/W 0 INTRTCEN request input 0: Disable 1: Enable 0 These bits should always be set to 11. TMP1942CY/CZ-23 TMP1942CY/CZ Note 1: When enabling an interrupt source as a means of terminating a standby mode, always set the active state for the corresponding interrupt request. Note 2: When using an interrupt, always perform the following steps in order: (1) Enable the input for the interrupt if the corresponding pin is also used for a general-purpose port or any other purpose. (2) Set the active state for the interrupt during initialization. (3) Clear the interrupt request. (4) Enable the interrupt. Note 3: The TMP1942 has eight interrupt sources (INT0~INT4, INTRTC, INTB/INTC/INTD/INTE, and KWUP0-KWUPD) which can be used as a means of terminating a standby mode. For INT0 to INT4, use the CG block to specify whether they are used to terminate a standby mode and to specify their active edge or level. For INTB/INTC/INTD/INTE and KWUP0-KWUPD, use the CG block to specify whether they are used to terminate a standby mode and use INTBCDEST and KWUPSTn, respectively, to specify their active edge or level. Set the active state for the corresponding interrupt source to High in the INTC block. Example: Enable the INT0 interrupt IMCGA0 All interrupt sources other than those which are used to terminate STOP/SLEEP mode are set in the INTC circuit block. Note 4: Among the above eight interrupt sources used to request the termination of a standby mode, INT0 to INT4 do not require settings in the CG block if they are used as normal interrupts. They still, however, require level or edge specification in the INTC. If INTB/INTC/INTD/INTE and KWUP0-KWUPD are used as normal interrupts, specify the active level or edge using INTBCDEST/KWUPSTn and specify the High level in the INTC. Settings in the CG are not required. INTRTC always requires settings in both the CG and INTC even if it is used as a normal interrupt. All interrupt sources other than those which are used to terminate a standby mode are set in the INTC circuit block. TMP1942CY/CZ-24 TMP1942CY/CZ (3) Interrupt request clear register 7 EICRCG Bit Symbol (0xFFFF_EE20) Read/Write After reset Function 6 5 4 3 2 ICRCG2 1 ICRCG1 W 0 ICRCG0 1 0 Clear interrupt request 000: INT0 100: INT4 001: INT1 101:KWUP 010: INT2 110: INTB/C/D/E 011: INT3 111: INTRTC Note : To clear any of the eight interrupt sources which are used for terminating a standby mode: (1) For KWUP, use KWUPCLR. (2) For extended interrupts INTB/INTC/INTD/INTE, use INTFLG. (3) For INT0 to INT4 and INTRTC, perform the clearing operation twice, first in the CG block and then in the INTC block. (4) For all other interrupt sources, use the INTC block. 3.3.3 System clock control unit When reset, the device enters single-clock mode with the result that XEN = 1, XTEN = 0 and GEAR1:0 = 11; the system clock fsys is set to fc/8 (= fc x 1/8). (Since the PLL multiplies the original oscillation frequency by 4, fc equals to fosc x 4, where fosc is the original oscillation frequency.) For example, if the X1 and X2 pins are connected to an 8-MHz resonator, a reset will set fsys to 4 MHz (= 8 MHz x 4 x 1/8). To disable the system from using a PLL-multiplied clock as the system clock by default, drive the PLLOFF pin Low. In this case, too, the system clock fsys will be set to fc/8 (= fc x 1/8) by a reset. However, since SYSCR1 TMP1942CY/CZ-25 TMP1942CY/CZ Note 1: Warm-up is unnecessary when the clock generator uses an oscillator so that its oscillation is stable. Note 2: Since the warm-up timer is clocked by an oscillating clock, it will not be exact if the oscillation frequency fluctuates. The warm-up time should, therefore, be considered to be an approximate value. Note 3: Before starting the warm-up timer, first confirm that the PLL lock-up flag (2 /oscillation frequency) (2 /oscillation frequency) (2 /oscillation frequency) (2 /oscillation frequency) 16 14 8 2 High-Speed Clock (fosc) 0.5 [s] 32 [s] 2.048 [ms] 8.192 [ms] Low-Speed Clock (fs) 122 [s] 7.8 [ms] 500 [ms] 2000 [ms] The values calculated are for when fosc = 8 MHz and fs = 32.768 kHz. Note: When returning from STOP/SLEEP mode to NORMAL or SLOW mode, set the warm-up time to 122 s or greater beforehand. Example: If the device will return from SLEEP mode to SLOW mode, set SYSCR2 SCOUT Selection NORMAL, SLOW Outputs fs clock. Outputs fsys clock. Standby Mode IDLE SLEEP STOP Fixed to 0 or 1 Note: This function does not guarantee a particular phase difference (AC timing) between the internal clock and the system clock output from SCOUT. TMP1942CY/CZ-26 TMP1942CY/CZ (3) Reducing the driving capability of oscillators If a resonator is connected to the resonator-connecting pins of an oscillator, this function can suppress oscillation noise output from the oscillator, while reducing power consumption by the oscillator. Setting SYSCR2 fOSC C1 Resonator SYSCR2 2) Reducing the driving capability of the low-speed oscillator C1 Resonator SYSCR2 3.3.4 Prescaler clock control unit The internal I/O blocks (TMRA01 to TMRAAB, TMRB0 to TMRBD, SIO0 to SIO5, SBI, and ADC) each incorporate a prescaler for dividing the clock frequency. The clock T0 fed into these prescalers is derived from the clock fperiph. fperiph is either fgear or fc (as specified by the value of SYSCR1 3.3.5 Clock multiplication circuit (PLL) This circuit multiplies the high-speed oscillator output clock, fosc, by 4 and outputs the result as the clock fpll. This enables the oscillator to yield a fast internal clock with a low oscillator frequency. The PLL is halted by a reset. To use the PLL, hold the PLLOFF pin High when terminating a reset. Note: If a reset is terminated while the PLLOFF pin is held Low, the PLL will not work and the internal clock chosen will be the original oscillating clock (i.e., it will not be multiplied by 4). TMP1942CY/CZ-27 TMP1942CY/CZ Since the PLL is configured as an analog circuit, it requires a certain settling time (a lock-up time) after it has been activated, as does the oscillator. The same timer is used for both warm-up and lock-up. The lock-up time must be set using SYSCR3 Precautions to be observed when switching clock gear: Clock gear switchover is performed by writing a value to SYSCR1 3.3.6 Standby control unit If the Halt bit in the TX19 processor core's Config register is set in NORMAL mode, the device enters one of the standby modes - IDLE, SLEEP or STOP - as determined by the contents of SYSCR2 TMP1942CY/CZ-28 TMP1942CY/CZ Table 3.3.3 IDLE Mode Internal I/O Setup Registers Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRA89 TMRAAB TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 TMRB8 TMRB9 TMRBA TMRBB TMRBC TMRBD SIO0 SIO1 SIO3 SIO4 SIO5 SBI A/D converter WDT IDLE Mode Setup Register TA01RUN Note 1: In Halt mode (entered when the Halt bit in the Config Register is set), the TX19 processor core stops processor operation while maintaining the pipeline status. Since it does not respond to requests for control of the bus from internal DMA, it retains control of the bus. Note 2: In Doze mode (entered when the Doze bit in the Config Register is set), the TX19 processor core stops processor operation while maintaining the pipeline status. In this mode, it can respond to requests for control of the bus from devices external to the processor core. 2) SLEEP: Only the internal low-speed oscillator, timer for real-time clock, 2-phase pulse input counter, and KWUP (dynamic pull-up) operate. 3) STOP: The CPU runs with the low-speed clock. The INTC, timer for real-time clock, WDT, 2-phase pulse input counter, KWUP (dynamic pull-up), PIO, and EBIF can operate. Operation of other peripheral functions is not guaranteed. 4) SLOW: All of the internal circuits stop. TMP1942CY/CZ-29 TMP1942CY/CZ (1) Operating status in each mode Table 3.3.4 Operating Status in Each Mode Operation Mode NORMAL IDLE (Halt) IDLE (Doze) SLEEP STOP Operating Status The TX19 processor core and peripheral I/O both operate at the maximum frequency. The TX19 processor core, INTC, timer for real-time clock, WDT, 2-phase pulse input counter, KWUP (dynamic pull-up), PIO, and EBIF operate with the low-speed clock. Processor operation stops and peripheral I/O operates as specified. Processor operation stops. Only the internal low-speed oscillator, timer for real-time clock, 2-phase pulse input counter, and KWUP (dynamic pull-up) operate (fs). Processor and peripheral I/O operation stops completely. (2) CG operation in each mode Table 3.3.5 CG Status in Each Operating Mode Clock Source Resonator Mode NORMAL SLOW IDLE (Halt) IDLE (Doze) SLEEP STOP Oscillator PLL fs only x x x x x x x Clock Supply to Peripheral I/O Clock Supply to the CPU Partially supplied (Note) Selectable Selectable Timer for real-time clock, 2-phase pulse input counter, and dynamic pull-up x x x x x x x x External input NORMAL SLOW IDLE (Halt) IDLE (Doze) SLEEP STOP x Partially supplied(Note) Selectable Selectable Timer for real-time clock, 2-phase pulse input counter, and dynamic pull-up x x x x x x x Note: This includes the INTC, EBIF (external bus interface), I/O ports, WDT, and timer for real-time clock. (3) Operation of circuit blocks in each mode (: Operating, x: Idle) Table 3.3.6 Circuit Block Operating Status in Each Mode Circuit Block TX19 processor core DMAC INTC EBIF External bus right PIO DA ADC SIO I2C Timer counter WDT 2-phase pulse input counter Dynamic pull-up Timer for real-time clock CG Fsys/fs Fs fs Clock Source IDLE (Doze) x IDLE (Halt) x x SLEEP x x x x x x x (*1) x x STOP x x x x x x x (*1) x x x x x x x x x fsys x Can be selected to run or stop for each module independently. x x x (fs only) *1: DAC output is controlled with the OP bit for each channel. TMP1942CY/CZ-30 TMP1942CY/CZ (4) Terminating a standby mode The device can be freed from a standby mode by an interrupt request or a reset. The combination of the interrupt mask register NMI Standby mode termination source Interrupt Enabled Interrupt Enabled (Interrupt level) > (Interrupt mask) (Interrupt level) (Interrupt mask) IDLE SLEEP STOP (programmable) *1 x x x x IDLE SLEEP (programmable) STOP INTWDT INT0~4, INTB~E KWUP0~D Interrupt *1 *1 x x x x x x x x x x x *1 *1 x x x x x x x INTRTC INT5~A INTTA0~B INTTB0~D INTRX0~5, TX0~5 INTS2 INTAD/ADHP/ADM (*2) x x x (*2) x x x RESET : After exiting the standby mode, the processor starts servicing the interrupt. (RESET initializes the LSI.) : After exiting the standby mode, the processor begins executing instructions starting with the one following the instruction to enter the standby mode, without servicing the interrupt. TMP1942CY/CZ-31 TMP1942CY/CZ x: Cannot be used to exit from a standby mode. *1: The device is actually released from the standby mode after the warm-up time has passed. *2: Only INTTB2 and INTTB3 can be used when 2-phase pulse input counter mode is selected. Note 1: When using a level-sensitive interrupt to terminate a standby mode, be sure to hold the level until the processor starts servicing the interrupt. If the level is changed before that time, the interrupt cannot be serviced properly. Note 2: If the interrupts are disabled in the CPU, use the interrupt controller (INTC) to disable only the interrupts other than those used for terminating standby, before placing the device in any of the standby modes. (5) STOP mode In STOP mode all internal circuits, including the internal oscillator, stop operating. The pin state in STOP mode varies according to the setting of SYSCR2 fsys (high-speed clock) Mode CG (high-speed clock) Warm-up (W-up) Warm-up started When fosc = 8 MHz W-up time selection SYSCR2 Stop Normal High-speed clock oscillation started Note: TMP1942CY/CZ-32 TMP1942CY/CZ 2) Operation mode transition from Normal through Sleep to Normal fsys (high-speed clock) Mode CG (high-speed clock) CG (low-speed clock) Warm-up (W-up) Warm-up started When fosc = 8 MHz W-up time selection SYSCR2 Sleep Normal W-up time (fc) Not allowed Not allowed 2.048 ms 8.192 ms Note: 3) Operation mode transition from Slow through Stop to Slow fsys (low-speed clock) Mode CG (low-speed clock) Warm-up (W-up) Warm-up started When fs = 32.768 MHz W-up time selection SYSCR2 Stop Slow Low-speed clock oscillation started 4) Operation mode transition from Slow through Sleep to Slow fsys (low-speed clock) Mode CG (low-speed clock) Warm-up (W-up) Warm-up started When fs = 32.768 MHz W-up time selection SYSCR2 Sleep Slow Low-speed clock continues oscillation. W-up time (fc) 122 s 7.8 ms 500 ms 2000 ms Note: fs continues oscillation but the warm-up time need be set. Set TMP1942CY/CZ-33 TMP1942CY/CZ Table 3.3.8 Pin States in STOP Mode (1/2) Pins AD0~AD7 AD8~AD15 A0~A7/A16~A23 , RD WR WAIT, BUSRQ HWR , BUSAK , R / W P37 P40~43 P44 (SCOUT) P50~57 P60~67 P90~P91 P92~97 PA0~PA1 PA2~PA7 PA7 PB1~PB4 PB0,PB5~PB6 PB7 PC0~PC5,PC7 PC6 PD0~PD5 PD6 (XT1)~ PD7 (XT2) Input/Output Input/Output Input/Output Output Output Input Output Output mode Input mode Output mode Input mode Output mode Input pin Input pin Input mode(KEY0~KEY7) Input mode Output mode Input mode(INT3,INT4) Input mode Output mode Input mode Output mode Input mode(INT3,INT4) Input mode Output mode Input mode Output mode Input mode(KEYA) Input mode Output mode Input mode(INTB~INTE) Input mode Output mode Input mode Output mode Input mode(KEYB) Input mode Output mode Input mode Output mode Input mode(KEYB) Input mode Output mode Input mode Output mode XT1, XT2 TMP1942CY/CZ-34 TMP1942CY/CZ Pins PE0~PE5 PE6~PE7 PF0,PF2~PF5 PF1 PF6 NMI ALE RESET BW0, BW1 X1 X2 Input/Output Input mode Output mode Input mode Output mode Input mode(INT1,INT2) Input mode Output mode Input mode Output mode Input mode(KEYD) Input mode Output mode Input mode(INT0) Input pin Output pin Input pin Input pin Input pin Output pin -: Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and output-only pins assume the high-Impedance state. Input: The input gate is active; the input voltage must be held at either the high or low level to keep the input pin from floating. Output: Pin direction is output. PU*: Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in high-impedance state. TMP1942CY/CZ-35 TMP1942CY/CZ 3.4 Interrupts Interrupts are controlled by the Status TMP1942CY/CZ-36 TMP1942CY/CZ CG INTnEN standby termination control Detection circuit INT04 5 8 Active High level INTC 8 High or Low level/edge setting High level 8 High level 1 1 High level Core 7 Other interrupts Active High level KWUP High or Low level/edge setting KEY0D Disable/enable each key input RTC Active High level Extended interrupts High or Low level/edge setting Disable/enable input for each interrupt source Note 1: Note 2: Note 3: Note 4: Standby termination is performed via the CG detection circuit. Since its output is a High-level active signal, the INTC must be set to accept a High-level active signal. The CG is bypassed for any processing other than standby termination. In that case, the active conditions for INT0 to INT4 must be set in the INTC. INTRTC requires CG settings for both standby termination and other processing. The INTC must be set to accept a High-level active signal. KWUP and INTB to INTD require settings in each circuit block for both standby termination and other processing. The INTC must be set to accept a High-level active signal. INTBE Figure 3.44.1 Interrupt Connection Diagram TMP1942CY/CZ-37 TMP1942CY/CZ (1) External interrupts INT0 to INT4, INTB to INTE, KWUP0 to KWUPD, and INTRTC 1) INT0 to INT4 When used to terminate a standby mode, these interrupts must have their active state set (using IMCGxx TMP1942CY/CZ-38 TMP1942CY/CZ (2) External interrupts INT5 to INTA and internal interrupt signals (other than INTRTC) All these interrupts must be set in the INTC block. The INTC resolves priority conflicts between interrupt sources and notifies the TX19 processor core of the interrupt with the highest priority. Interrupt INT0INT4, INTRTC* Register to be Set IMCGx reg.In CG IMCx reg.In INTC Usable Interrupt Detection Level When used to terminate a standby mode, the interrupt source active state must be set to High in the INTC block. The active state of these interrupts must be selected in the CG. However, when these interrupts are not used to terminate a standby mode, their active state must be selected in the INTC block. In both cases, Low level, High level, falling edge and rising edge are all acceptable. The interrupt source active state must always be set to High in the INTC block. When these interrupts are used to terminate a standby mode, the interrupt source active state must also be set to High in the CG. The active state of these interrupts must be selected in INTnST. However, when these interrupts are not used to terminate a standby mode, settings in the CG are not necessary. In both cases, Low level, High level, falling edge and rising edge are all acceptable. The interrupt source active state must always be set to High in the INTC block. When these interrupts are used to terminate a standby mode, the interrupt source active state must also be set to High in the CG. The active state of these interrupts must be selected in KWUPSTn. However, when these interrupts are not used to terminate a standby mode, settings in the CG are not necessary. In both cases, Low level, High level, falling edge and rising edge are all acceptable. Low level, High level, falling edge and rising edge are all acceptable in the INTC. Falling edge Rising edge INTBINTE IMCGx reg.In CG IMCx reg.In INTC INTnST KWUP0D IMCGx reg.In CG IMCx reg.In INTC KWUPSTn INT5INTA Internal I/O INTDMAn Others IMCx reg.In INTC IMCx reg.In INTC IMCx reg.In INTC Note 1: Interrupt level 0 indicates that the corresponding interrupt is disabled. Note 2: Only a rising edge can be used for INTRTC. * Example interrupt settings When INT0 is used to request the termination of STOP/SLEEP mode (falling edge) a. Enabling the interrupt IMCGA0 : Select falling edge for INT0 : Clear interrupt request for INT0 : Enable request input for INT0 : Select High level for INT0 : Clear interrupt request for INT0 : Set interrupt level to 5 CG block INTC block TX19 processor core TX19 processor core : Disable interrupt for INT0 : Clear interrupt request for INT0 : Disable request input for INT0 : Clear interrupt request for INT0 INTC block CG block TMP1942CY/CZ-39 TMP1942CY/CZ 3.4.1 Interrupt sources (1) Reset and non-maskable interrupts: RESET , NMI and INTWDT (watchdog timer interrupt) Vector address: 0xBFC0_0000 (virtual address) (2) Maskable interrupts: Software and hardware interrupts Vector addresses: 0xBFC0_0210 (virtual address) to 0xBFC0_0260 (virtual address) Interrupt Source Reset Non-maskable Software Maskable Vector Address (virtual address) 0xBFC0_0000 Swi0 Swi1 Swi2 Swi3 0xBFC0_0210 0xBFC0_0220 0xBFC0_0230 0xBFC0_0240 0xBFC0_0260 Hardware Note 1: When vector addresses are located in the on-chip ROM, set the BEV bit in the system control coprocessor (CP0) Status register to 1. Note 2: Maskable software interrupts are generated by setting TMP1942CY/CZ-40 TMP1942CY/CZ Table 3.44.1 Hardware Interrupt Sources Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 IVR[9 : 0] 000 010 020 030 040 050 060 070 080 090 0A0 0B0 0C0 0D0 0E0 0F0 100 110 120 130 140 150 160 170 180 190 1A0 1B0 1C0 1D0 1E0 1F0 200 210 220 230 240 250 260 270 280 290 2A0 2B0 2C0 2D0 2E0 2F0 300 310 320 330 340 350 360 370 380 390 3A0 3B0 3C0 3D0 3E0 3F0 Interrupt Source Software Set INT0 pin (standby termination) INT1 pin (standby termination) INT2 pin (standby termination) INT3 pin (standby termination) INT4 pin (standby termination) KWUP (standby termination) INTB/C/D/E pin (standby termination) Reserved Reserved INT5 pin INT6 pin INT7 pin INT8 pin INT9 pin INTA pin INTRX0: Serial reception (channel 0) INTTX0: Serial transmission (channel 0) INTRX1: Serial reception (channel 1) INTTX1: Serial transmission (channel 1) INTS2: Serial channel 2 interrupt INTRX3: Serial reception (channel 3) INTTX3: Serial transmission (channel 3) INTADHP: Highest-priority A/D conversion completed INTADM: A/D conversion monitor interrupt INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 1 INTRX4: Serial reception (channel 4) INTTX4: Serial transmission (channel 4) INTRX5: Serial reception (channel 5) INTTX5: Serial transmission (channel 5) Reserved Reserved INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTA6: 8-bit timer 6 INTTA7: 8-bit timer 7 INTTA8: 8-bit timer 8 INTTA9: 8-bit timer 9 INTTAA: 8-bit timer A INTTAB: 8-bit timer B INTTBA: 16-bit timer A INTTBB: 16-bit timer B INTTBC: 16-bit timer C INTTBD: 16-bit timer D INTTB2: 16-bit timer 2 INTTB3: 16-bit timer 3 INTTB4: 16-bit timer 4 INTTB5: 16-bit timer 5 INTTB6: 16-bit timer 6 INTTB7: 16-bit timer 7 INTTB8: 16-bit timer 8 INTTB9: 16-bit timer 9 Reserved INTRTC: Interrupt from timer for real-time clock INTAD: A/D conversion completed INTDMA0: DMA transfer completed (channel 0) INTDMA1: DMA transfer completed (channel 1) INTDMA2: DMA transfer completed (channel 2) INTDMA3: DMA transfer completed (channel 3) Interrupt control register IMC0L IMC0H IMC1L IMC1H IMC2L IMC2H IMC3L IMC3H IMC4L IMC4H IMC5L IMC5H IMC6L IMC6H IMC7L IMC7H IMC8L IMC8H IMC9L IMC9H IMCAL IMCAH IMCBL IMCBH IMCCL IMCCH IMCDL IMCDH IMCEL IMCEH IMCFL IMCFH Address 0xFFFF_E000 0xFFFF_E002 0xFFFF_E004 0xFFFF_E006 0xFFFF_E008 0xFFFF_E00A 0xFFFF_E00C 0xFFFF_E00E 0xFFFF_E010 0xFFFF_E012 0xFFFF_E014 0xFFFF_E016 0xFFFF_E018 0xFFFF_E01A 0xFFFF_E01C 0xFFFF_E01E 0xFFFF_E020 0xFFFF_E022 0xFFFF_E024 0xFFFF_E026 0xFFFF_E028 0xFFFF_E02A 0xFFFF_E02C 0xFFFF_E02E 0xFFFF_E030 0xFFFF_E032 0xFFFF_E034 0xFFFF_E036 0xFFFF_E038 0xFFFF_E03A 0xFFFF_E03C 0xFFFF_E03E TMP1942CY/CZ-41 TMP1942CY/CZ 3.4.2 Interrupt detection When using interrupts to terminate a standby mode, the following settings are necessary according to the interrupt type: Interrupts INT0 to INT4 have their active state set using the EMCGxx field in the CG's internal IMCGxx register, then the EIMxx field in the INTC's internal IMCx register is set to High. Extended interrupts INTB to INTE have their active state set to High using the EMCG field in the CG's internal IMCGB2 register, then the EIMxx field in the INTC's internal IMCx register is set to High. In addition, INTnST is used to set the active state for each interrupt source and enable/disable the interrupt source. KWUP0 to KWUPD have their active state set to High using the EMCG field in the CG's internal IMCGB1 register, then the EIMxx field in the INTC's internal IMCx register is set to High. In addition, KWUPSTn is used to set the active state for each interrupt source and enable/disable the interrupt source. The RTC interrupt has its active state set to a rising edge using the EMCGxx field in the CG's internal IMCGxx register, then the EIMxx field in the INTC's internal IMCx register is set to High. Other interrupts have their active state set using only the EIMxx field in the INTC's internal IMCx register. The active state can be one of the following four: rising edge, falling edge, High level or Low level. When the TMP1942 detection circuit recognizes the active state of an interrupt request set in this way, it notifies the processor core or the INTC of the interrupt request. When the above interrupts are not used to terminate a standby mode, settings in the CG are not required: INT0 to INT4 require only settings in the INTC, INTB to INTE require the same settings in the INTC as for standby termination as well as setting in INTnST, and KWUP0 to KWUPD require the same settings in the INTC as for standby termination as well as setting in KWUPSTn. Cancellation of interrupt signals is carried out by the interrupt handler after it has recognized the requested interrupt. INTB to INTE are canceled by reading INTFLG. Interrupt signals from INT0 to INT4 and INTRTC are cancelled by writing the appropriate value to the ICRCG field in the CG's internal EICRCG register and then writing the corresponding value to the EICLR field in the INTC's internal INTCLR register. KWUP0 to KWUPD are canceled by setting KWUPCLR. Other interrupt signals are canceled by writing the appropriate value to the EICLR field in the INTC's internal INTCLR register. These cancellation procedures apply regardless of whether the active state is an edge or level. TMP1942CY/CZ-42 TMP1942CY/CZ Start NO Standby termination INTBE KWUP0D YES INT04 INTRTC Interrupt? INTBE KWUP0D Interrupt? INT0A/ INTRTC* Set INTC Set CG Set KWUPSTn or INTnST Set INTC (High level) Set INTC (High level) Set KWUPSTn or INTnST Set CG (High level) Set INTC (High level) End * The INTRTC interrupt must have its active state set to a rising edge in the CG even when it is not used for standby termination. Figure 3.44.2 Flow for Setting External Interrupts Note: Each stage must be completed in the following sequence: set the active level, clear the interrupt request, and then enable the interrupt. (Example of setting INT0 for standby termination) IMCGA0 TMP1942CY/CZ-43 TMP1942CY/CZ 3.4.3 Resolving interrupt priority (1) Seven interrupt priority levels The TMP1942 has seven interrupt priority levels; thus for each interrupt source the priority can be set to one of seven levels. The interrupt mode control register (IMCx) is used for setting interrupt levels. This register includes a 3-bit level-setting field (ILx). The greater the value (interrupt level) set in IMC TMP1942CY/CZ-44 TMP1942CY/CZ 3.4.4 INTC registers Table 3.44.2 INTC Register Map Address 0xFFFF_E060 0xFFFF_E040 0xFFFF_E03C 0xFFFF_E038 0xFFFF_E034 0xFFFF_E030 0xFFFF_E02C 0xFFFF_E028 0xFFFF_E024 0xFFFF_E020 0xFFFF_E01C 0xFFFF_E018 0xFFFF_E014 0xFFFF_E010 0xFFFF_E00C 0xFFFF_E008 0xFFFF_E004 0xFFFF_E000 Register Symbol INTCLR IVR IMCF IMCE IMCD IMCC IMCB IMCA IMC9 IMC8 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1 IMC0 Register Interrupt request clear control Interrupt vector register Interrupt mode control register F Interrupt mode control register E Interrupt mode control register D Interrupt mode control register C Interrupt mode control register B Interrupt mode control register A Interrupt mode control register 9 Interrupt mode control register 8 Interrupt mode control register 7 Interrupt mode control register 6 Interrupt mode control register 5 Interrupt mode control register 4 Interrupt mode control register 3 Interrupt mode control register 2 Interrupt mode control register 1 Interrupt mode control register 0 Corresponding Interrupt Number ALL (63 - 0) ALL (63 - 0) 63 - 60 59 - 56 55 - 52 51 - 48 47 - 44 43 - 40 39 - 36 35 - 32 31 - 28 27 - 24 23 - 20 19 - 16 15 - 12 11 - 8 7-4 3-0 Interrupt vector register (IVR): Indicates the vector for the source of each interrupt generated. 7 IVR Bit Symbol After reset Function IVR7 0 (0xFFFF_E040) Read/Write 0 0 0 Indicates the vectors for generated interrupt sources. 6 IVR6 5 IVR5 4 IVR4 R 3 2 1 0 0 0 0 0 15 Bit Symbol Read/Write After reset Function 0 14 13 R/W 12 11 10 9 IVR9 R 8 IVR8 0 0 0 0 0 0 0 Indicates the vectors for generated interrupt sources. 23 Bit Symbol Read/Write After reset Function 0 22 21 20 R/W 19 18 17 16 0 0 0 0 0 0 0 31 Bit Symbol Read/Write After reset Function 0 30 29 28 R/W 27 26 25 24 0 0 0 0 0 0 0 TMP1942CY/CZ-45 TMP1942CY/CZ Interrupt mode control registers: Set the priority level and active state for each interrupt source and set whether the interrupt is to be used to activate the DMAC. 7 IMC0 Bit Symbol After reset Function (0xFFFF_E000) Read/Write 0 0 0 Sets whether or not to activate the DMAC. 0: Not set. 6 5 EIM01 4 EIM00 3 DM0 R/W 2 IL02 0 1 IL01 0 0 IL00 0 Sets the active state of the interrupt request. 00: Low level Other settings are not allowed. Sets the priority level for interrupt number 0 (Software Set) when DM0 = 0. 000: Disable interrupt. 001-111: 1 to 7 Selects a DMAC channel when 1: Set interrupt DM0 = 1. number 0 to 000-011: 0 to 3 activate the DMAC. 100-111: Invalid settings 15 Bit Symbol Read/Write After reset Function 14 13 EIM11 0 12 EIM10 0 11 DM1 R/W 0 Sets whether or not to activate the DMAC. 0: Not set. 10 IL12 0 9 IL11 0 8 IL10 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge Sets the priority level for interrupt number 1 (INT0) when DM1 = 0. 000: Disable interrupt. 001-111: 1 to 7 Selects a DMAC channel when 1: Set interrupt DM1 = 1. number 1 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM21 0 20 EIM20 0 19 DM2 R/W 0 Sets whether or not to activate the DMAC. 0: Not set. 18 IL22 0 17 IL21 0 16 IL20 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge Sets the priority level for interrupt number 2 (INT1) when DM2 = 0. 000: Disable interrupt. 001-111: 1 to 7 Selects a DMAC channel when 1: Set interrupt DM2 = 1. number 2 to 000-011: 0 to 3 activate the DMAC. 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIM31 0 28 EIM30 0 27 DM3 R/W 0 Sets whether or not to activate the DMAC. 26 IL32 0 25 IL31 0 24 IL30 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge Sets the priority level for interrupt number 3 (INT2) when DM3 = 0. 000: Disable interrupt. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set interrupt DM3 = 1. number 3 to 000-011: 0 to 3 activate the DMAC. 100-111: Invalid settings Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-46 TMP1942CY/CZ 7 IMC1 (0xFFFF_E004) Bit Symbol Read/Write After reset Function 6 5 EIM41 4 EIM40 3 DM4 R/W 2 IL42 1 IL41 0 IL40 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 4 (INT3) when not to DM4 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM4 = 1. interrupt 000-011: 0 to 3 number 4 to 100-111: Invalid settings activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM51 12 EIM50 11 DM5 R/W 0 10 IL52 9 IL51 8 IL50 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 Sets Sets the priority level for interrupt whether or number 5 (INT4) when not to DM5 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM5 = 1. interrupt 000-011: 0 to 3 number 5 to activate the DMAC. 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM61 20 EIM60 19 DM6 R/W 0 18 IL62 17 IL61 16 IL60 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 Sets Sets the priority level for interrupt whether or number 6 (KWUP) when not to DM6 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM6 = 1. interrupt number 6 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIM71 28 EIM70 27 DM7 R/W 0 26 IL72 25 IL71 24 IL70 0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 Sets Sets the priority level for interrupt whether or number 7 (INTB/C/D/E) when not to DM7 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM7 = 1. interrupt 000-011: 0 to 3 number 7 to 100-111: Invalid settings activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-47 TMP1942CY/CZ 7 IMC2 (0xFFFF_E008) Bit Symbol Read/Write After reset Function 6 5 EIM81 0 4 EIM80 0 3 DM8 R/W 0 Must be set to 0. 2 IL82 0 1 IL81 0 0 IL80 0 Must be set to 00. Must be set to 000. 15 Bit Symbol Read/Write After reset Function 14 13 EIM91 0 12 EIM90 0 11 DM9 R/W 0 Must be set to 0. 10 IL92 0 9 IL91 0 8 IL90 0 Must be set to 00. Must be set to 000. 23 Bit Symbol Read/Write After reset Function 22 21 EIMA1 20 EIMA0 19 DMA R/W 18 ILA2 17 ILA1 16 ILA0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 0 Sets Sets the priority level for interrupt whether or number 10 (INT5) when not to DMA = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DMA = 1. interrupt number 10 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIMB1 28 EIMB0 27 DMB R/W 26 ILB2 25 ILB1 24 ILB0 0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 0 Sets Sets the priority level for interrupt whether or number 11 (INT6) when not to DMB = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DMB = 1. interrupt 000-011: 0 to 3 number 11 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-48 TMP1942CY/CZ 7 IMC3 (0xFFFF_E00C) Bit Symbol Read/Write After reset Function 6 5 EIMC1 4 EIMC0 3 DMC R/W 2 ILC2 1 ILC1 0 ILC0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 12 (INT7) when not to DMC = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DMC = 1. interrupt 000-011: 0 to 3 number 12 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIMD1 12 EIMD0 11 DMD R/W 0 10 ILD2 9 ILD1 8 ILD0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 Sets Sets the priority level for interrupt whether or number 13 (INT8) when not to DMD = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DMD = 1. interrupt 000-011: 0 to 3 number 13 to activate the DMAC. 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIME1 20 EIME0 19 DME R/W 18 ILE2 17 ILE1 16 ILE0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 0 Sets Sets the priority level for interrupt whether or number 14 (INT9) when not to DME = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DME = 1. interrupt number 14 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIMF1 28 EIMF0 27 DMF R/W 26 ILF2 25 ILF1 24 ILF0 0 0 0 Sets the active state of the interrupt request. 00: Low level 01: High level 10: Falling edge 11: Rising edge 0 0 0 0 Sets Sets the priority level for interrupt whether or number 15 (INTA) when not to DMF = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DMF = 1. interrupt 000-011: 0 to 3 number 15 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-49 TMP1942CY/CZ 7 IMC4 (0xFFFF_E010) Bit Symbol Read/Write After reset Function 6 5 EIM101 0 4 EIM100 0 3 DM10 R/W 2 IL102 1 IL101 0 IL100 Must be set to 11. 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 16 (INTRX0) when not to DM10 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM10 = 1. interrupt 000-011: 0 to 3 number 16 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM111 0 12 EIM110 0 11 DM11 R/W 0 10 IL112 9 IL111 8 IL110 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 16 (INTTX0) when not to DM11 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM11 = 1. interrupt 000-011: 0 to 3 number 17 to activate the DMAC. 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM121 0 20 EIM120 0 19 DM12 R/W 18 IL122 17 IL121 16 IL120 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 18 (INTRX1) when not to DM12 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM12 = 1. interrupt number 18 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIM131 28 EIM130 0 27 DM13 R/W 26 IL132 25 IL131 24 IL130 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 19 (INTTX1) when not to DM13 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM13 = 1. interrupt 000-011: 0 to 3 number 19 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-50 TMP1942CY/CZ 7 IMC5 (0xFFFF_E014) Bit Symbol Read/Write After reset Function 6 5 EIM141 0 4 EIM140 0 3 DM14 R/W 2 IL142 1 IL141 0 IL140 Must be set to 11. 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 20 (INTS2) when not to DM14 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM14 = 1. interrupt 000-011: 0 to 3 number 20 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM151 0 12 EIM150 0 11 DM15 R/W 10 IL152 9 IL151 8 IL150 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 21 (INTRX3) when not to DM15 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM15 = 1. interrupt number 21 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM161 0 20 EIM160 0 19 DM16 R/W 0 18 IL162 17 IL161 16 IL160 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 22 (INTTX3) when not to DM16 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM16 = 1. interrupt 000-011: 0 to 3 number 22 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM171 28 EIM170 0 27 DM17 R/W 0 26 IL172 25 IL171 24 IL170 0 0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 23 (INTADHP) when not to DM17 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM17 = 1. interrupt 000-011: 0 to 3 number 23 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-51 TMP1942CY/CZ 7 IMC6 (0xFFFF_E018) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM181 4 EIM180 3 DM18 R/W 2 IL182 1 IL181 0 IL180 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 24 (INTADM) when not to DM18 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM18 = 1. interrupt 000-011: 0 to 3 number 24 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM191 0 12 EIM190 0 11 DM19 R/W 0 10 IL192 9 IL191 8 IL190 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 25 (INTTA0) when not to DM19 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM19 = 1. interrupt number 25 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM1A1 0 20 EIM1A0 0 19 DM1A R/W 0 18 IL1A2 17 IL1A1 16 IL1A0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 26 (INTTA1) when not to DM1A = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM1A = 1. interrupt 000-011: 0 to 3 number 26 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM1B1 28 EIM1B0 0 27 DM1B R/W 26 IL1B2 25 IL1B1 24 IL1B0 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 27 (INTTA2) when not to DM1B = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM1B = 1. interrupt 000-011: 0 to 3 number 27 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-52 TMP1942CY/CZ 7 IMC7 (0xFFFF_E01C) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM1C1 4 EIM1C0 3 DM1C R/W 2 IL1C2 1 IL1C1 0 IL1C0 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 28 (INTTA3) when not to DM1C = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM1C = 1. interrupt 000-011: 0 to 3 number 28 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM1D1 0 12 EIM1D0 0 11 DM1D R/W 0 10 IL1D2 9 IL1D1 8 IL1D0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 29 (INTTB0) when not to DM1D = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM1D = 1. interrupt number 29 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM1E1 0 20 EIM1E0 0 19 DM1E R/W 0 18 IL1E2 17 IL1E1 16 IL1E0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 30 (INTTB1) when not to DM1E = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM1E = 1. interrupt 000-011: 0 to 3 number 30 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM1F1 28 EIM1F0 0 27 DM1F R/W 26 IL1F2 25 IL1F1 24 IL1F0 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 31 (INTRX4) when not to DM1F = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM1F = 1. interrupt 000-011: 0 to 3 number 31 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-53 TMP1942CY/CZ 7 IMC8 (0xFFFF_E020) Bit Symbol Read/Write After reset Function 6 5 EIM201 0 4 EIM200 0 3 DM20 R/W 2 IL202 1 IL201 0 IL200 Must be set to 11. 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 32 (INTTX4) when not to DM20 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM20 = 1. interrupt 000-011: 0 to 3 number 32 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM211 0 12 EIM210 0 11 DM21 R/W 10 IL212 9 IL211 8 IL210 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 33 (INTRX5) when not to DM21 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM21 = 1. interrupt number 33 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM221 0 20 EIM220 0 19 DM22 R/W 0 18 IL222 17 IL221 16 IL220 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 34 (INTTX5) when not to DM22 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM22 = 1. interrupt 000-011: 0 to 3 number 34 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM231 28 EIM230 0 27 DM23 R/W 0 Must be set to 0. 26 IL232 0 25 IL231 0 24 IL230 0 0 0 Must be set to 00. Must be set to 000. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-54 TMP1942CY/CZ 7 IMC9 (0xFFFF_E024) Bit Symbol Read/Write After reset Function 0 0 0 Must be set to 0. Must be set to 00. 6 5 EIM241 4 EIM240 3 DM24 R/W 2 IL242 0 1 IL241 0 0 IL240 0 Must be set to 000. 15 Bit Symbol Read/Write After reset Function 14 13 EIM251 0 12 EIM250 0 11 DM25 R/W 10 IL252 9 IL251 8 IL250 Must be set to 11. 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 37 (INTTA4) when not to DM25 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM25 = 1. interrupt 000-011: 0 to 3 number 37 100-111: Invalid settings to activate the DMAC. 23 Bit Symbol Read/Write After reset Function 22 21 EIM261 0 20 EIM260 0 19 DM26 R/W 18 IL262 17 IL261 16 IL260 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 38 (INTTA5) when not to DM26 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM26 = 1. interrupt number 38 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIM271 28 EIM270 0 27 DM27 R/W 0 26 IL272 25 IL271 24 IL270 0 0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 39 (INTTA6) when not to DM27 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM27 = 1. interrupt number 39 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-55 TMP1942CY/CZ 7 IMCA (0xFFFF_E028) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM281 4 EIM280 3 DM28 R/W 2 IL282 1 IL281 0 IL280 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 40 (INTTA7) when not to DM28 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM28 = 1. interrupt 000-011: 0 to 3 number 40 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM291 0 12 EIM290 0 11 DM29 R/W 0 10 IL292 9 IL291 8 IL290 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 41 (INTTA8) when not to DM29 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM29 = 1. interrupt number 41 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM2A1 0 20 EIM2A0 0 19 DM2A R/W 0 18 IL2A2 17 IL2A1 16 IL2A0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 42 (INTTA9) when not to DM2A = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM2A = 1. interrupt 000-011: 0 to 3 number 42 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM2B1 28 EIM2B0 0 27 DM2B R/W 26 IL2B2 25 IL2B1 24 IL2B0 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 43 (INTTAA) when not to DM2B = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM2B = 1. interrupt 000-011: 0 to 3 number 43 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-56 TMP1942CY/CZ 7 IMCB (0xFFFF_E02C) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM2C1 4 EIM2C0 3 DM2C R/W 2 IL2C2 1 IL2C1 0 IL2C0 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 44 (INTTAB) when not to DM2C = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM2C = 1. interrupt 000-011: 0 to 3 number 44 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM2D1 0 12 EIM2D0 0 11 DM2D R/W 0 10 IL2D2 9 IL2D1 8 IL2D0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 45 (INTTBA) when not to DM2D = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM2D = 1. interrupt number 45 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM2E1 0 20 EIM2E0 0 19 DM2E R/W 0 18 IL2E2 17 IL2E1 16 IL2E0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 46 (INTTBB) when not to DM2E = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM2E = 1. interrupt 000-011: 0 to 3 number 46 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM2F1 28 EIM2F0 0 27 DM2F R/W 26 IL2F2 25 IL2F1 24 IL2F0 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 47 (INTTBC) when not to DM2F = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM2F = 1. interrupt 000-011: 0 to 3 number 47 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-57 TMP1942CY/CZ 7 IMCC (0xFFFF_E030) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM301 4 EIM300 3 DM30 R/W 2 IL302 1 IL301 0 IL300 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 48 (INTTBD) when not to DM30 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM30 = 1. interrupt 000-011: 0 to 3 number 48 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM311 0 12 EIM310 0 11 DM31 R/W 0 10 IL312 9 IL311 8 IL310 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 49 (INTTB2) when not to DM31 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM31 = 1. interrupt number 49 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM321 0 20 EIM320 0 19 DM32 R/W 0 18 IL322 17 IL321 16 IL320 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 50 (INTTB3) when not to DM32 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM32 = 1. interrupt 000-011: 0 to 3 number 50 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM331 28 EIM330 0 27 DM33 R/W 26 IL332 25 IL331 24 IL330 0 0 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 51 (INTTB4) when not to DM33 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM33 = 1. interrupt 000-011: 0 to 3 number 51 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-58 TMP1942CY/CZ 7 IMCD (0xFFFF_E034) Bit Symbol Read/Write After reset Function 6 5 EIM341 0 4 EIM340 0 3 DM34 R/W 2 IL342 1 IL341 0 IL340 Must be set to 11. 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 52 (INTTB5) when not to DM34 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM34 = 1. interrupt 000-011: 0 to 3 number 52 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM351 0 12 EIM350 0 11 DM35 R/W 10 IL352 9 IL351 8 IL350 Must be set to 11. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 53 (INTTB6) when not to DM35 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM35 = 1. interrupt number 53 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM361 0 20 EIM360 0 19 DM36 R/W 0 18 IL362 17 IL361 16 IL360 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 54 (INTTB7) when not to DM36 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM36 = 1. interrupt 000-011: 0 to 3 number 54 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM371 28 EIM370 0 27 DM37 R/W 0 26 IL372 25 IL371 24 IL370 0 0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 55 (INTTB8) when not to DM37 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM37 = 1. interrupt 000-011: 0 to 3 number 55 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-59 TMP1942CY/CZ 7 IMCE (0xFFFF_E038) Bit Symbol Read/Write After reset Function 0 0 Must be set to 11. 6 5 EIM381 4 EIM380 3 DM38 R/W 2 IL382 1 IL381 0 IL380 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 56 (INTTB9) when not to DM38 = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM38 = 1. interrupt 000-011: 0 to 3 number 56 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM391 0 12 EIM390 0 11 DM39 R/W 0 Must be set to 0. 10 IL392 0 9 IL391 0 8 IL390 0 Must be set to 00. Must be set to 000. 23 Bit Symbol Read/Write After reset Function 22 21 EIM3A1 0 20 EIM3A0 0 19 DM3A R/W 18 IL3A2 17 IL3A1 16 IL3A0 Must be set to 01. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 58 (INTRTC) when not to DM3A = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM3A = 1. interrupt number 58 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 31 Bit Symbol Read/Write After reset Function 30 29 EIM3B1 28 EIM3B0 0 27 DM3B R/W 0 26 IL3B2 25 IL3B1 24 IL3B0 0 0 Must be set to 11. 0 0 0 Sets Sets the priority level for interrupt whether or number 59 (INTAD) when not to DM3B = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM3B = 1. interrupt number 59 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-60 TMP1942CY/CZ 7 IMCF (0xFFFF_E03C) Bit Symbol Read/Write After reset Function 0 0 Must be set to 10. 6 5 EIM3C1 4 EIM3C0 3 DM3C R/W 2 IL3C2 1 IL3C1 0 IL3C0 0: Not set. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 60 (INTDMA0) when not to DM3C = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 Selects a DMAC channel when 1: Set DM3C = 1. interrupt 000-011: 0 to 3 number 60 100-111: Invalid settings to activate the DMAC. 15 Bit Symbol Read/Write After reset Function 14 13 EIM3D1 0 12 EIM3D0 0 11 DM3D R/W 0 10 IL3D2 9 IL3D1 8 IL3D0 Must be set to 10. 0 0 0 Sets Sets the priority level for interrupt whether or number 61 (INTDMA1) when not to DM3D = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM3D = 1. interrupt number 61 to activate the DMAC. 000-011: 0 to 3 100-111: Invalid settings 23 Bit Symbol Read/Write After reset Function 22 21 EIM3E1 0 20 EIM3E0 0 19 DM3E R/W 0 18 IL3E2 17 IL3E1 16 IL3E0 Must be set to 10. 0 0 0 Sets Sets the priority level for interrupt whether or number 62 (INTDMA1) when not to DM3E = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM3E = 1. interrupt 000-011: 0 to 3 number 62 100-111: Invalid settings to activate the DMAC. 31 Bit Symbol Read/Write After reset Function 30 29 EIM3F1 28 EIM3F0 0 27 DM3F R/W 26 IL3F2 25 IL3F1 24 IL3F0 0 0 Must be set to 10. 0 0 0 0 Sets Sets the priority level for interrupt whether or number 63 (INTDMA2) when not to DM3F = 0. activate the 000: Disable interrupt. DMAC. 001-111: 1 to 7 0: Not set. Selects a DMAC channel when 1: Set DM3F = 1. interrupt 000-011: 0 to 3 number 63 100-111: Invalid settings to activate the DMAC. Note : Before enabling the above interrupt requests, be sure to set their active state. TMP1942CY/CZ-61 TMP1942CY/CZ Interrupt request clear register: Sets the value of IVR INTCLR Bit Symbol After reset Function 6 5 EICLR5 4 EICLR4 3 EICLR3 W 2 EICLR2 1 EICLR1 0 EICLR0 (0xFFFF_E060) Read/Write Sets the value of IVR<9:4> for the interrupt whose request is to be cleared. Note1: Do not clear an interrupt request before reading the corresponding IVR value. Note2: Follow the steps below to disable a particular interrupt with the Interrupt Controller (INTC). 1. Globally disable the acceptance of interrupts by the core processor by clearing the IEc bit of the Status register. 2. Disable the desired interrupt with the INTC by clearing the ILx[2:0] field of the IMCxx register. 3. Execute the SYNC instruction. 4. Enable the acceptance of interrupts by the core processor by setting the IEc bit of the Status register. Example: mtc0 sb sync mtc0 $sp, r31 r0, r31 r0, IMC** ; _DI () ; ; IMC** = 0 ; ; _SYNC () ; ; _EI () ; TMP1942CY/CZ-62 TMP1942CY/CZ 3.5 I/O Ports The TMP1942 has 108 I/O port pins. All the port pins except a few share pins with alternate functions. They can be individually programmed as general-purpose I/O or dedicated I/O for the on-chip CPU or peripherals. Table 3.5.1 Programmable I/O Ports(1/2) Port Port 0 Port 1 Port 2 Pin Name P00~P07 P10~P17 P20~P27 P30 P31 P32 Port 3 P33 P34 P35 P36 P37 P40 P41 Port 4 P42 P43 P44 Port 5 Port 6 P50~P57 P60~P67 P90 P91 P92 P93 Port 9 P94 P95 P96 P97 # of Pins 8 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 8 8 1 1 1 1 1 1 1 1 Direction Input/output Input/output Input/output Output Output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull up Pull Resistor Direction Programmability Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Fixed Fixed Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise AD0~AD7 AD8~AD15 A0~A7 RD WR HWR WAIT BUSRQ BUSAK R/W DSU CS0 CS1 CS2 CS3 SCOUT AN0~AN7 AN8~AN15 KEY8 KEY9 TB40UT TB5OUT TB6OUT TB7IN0 TB7IN1 TB7OUT ADTRG KEY0-KEY7 A8~A15 A16~A23 Alternate Functions TMP1942CY/CZ-63 TMP1942CY/CZ Table 3.5.1 Programmable I/O Ports(2/2) Port Pin Name PA0 PA1 PA2 Port A PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 Port B PB4 PB5 PB6 PB7 PC0 PC1 PC2 Port C PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 Port D PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 Port E PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 Port F PF3 PF4 PF5 PF6 # of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Pull Resistor Direction Programmability Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise Bitwise bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit Alternate Functions TB0IN0 TB0IN1 TB0OUT TB1IN0 TB1IN1 TB1OUT TA1OUT TA0IN TB2IN0 TB2IN1 TB2OUT TB3IN0 TB3IN1 TB3OUT TA3OUT TA2IN TA4IN TA6IN TA8IN TA5OUT TAAIN TA7OUT TB8IN0 TB8IN1 TXD0 RXD0 SCLK0 TXD1 RXD1 SCLK1 XT1 XT2 TXD3 RXD3 SCLK3 TXD4 RXD4 SCLK4 INT1 INT2 TXD5 RXD5 SCLK5 SCK SO SI INT0 SDA SCL CTS4 BOOT INTLV KEYD CTS5 KEYC TA9OUT TB9IN0 TB9IN1 CTS0 TBAIN0 TBAIN1 CTS1 TABOUT INT7 INT8 INT9 INTA KEYB KEYA INTB INTC TB4IN0 INTD INTE TB4IN1 INT5 INT6 INT3 INT4 CTS3 TMP1942CY/CZ-64 TMP1942CY/CZ Table 3.5.2 I/O Port Programmability (1/4) Port Pin Name Direction / Function Input Port 0 P00~P07 Output AD0~AD7 Bus Input Port 1 P10~P17 Output AD8~AD15 Bus A8~A15 Bus Input Port 2 P20~P27 Output A0~A7 Bus A16~A23 Bus P30 P31 Output RD Output WR Input(RSTUP=1) P32 Input(RSTUP=0) Output HWR Input(RSTUP=1) P33 Input(RSTUP=0) Output WAIT Input(RSTUP=1) P34 Input(RSTUP=0) Output BUSRQ Input(RSTUP=1) P35 Input(RSTUP=0) Output BUSAK Input(RSTUP=1) P36 Input(RSTUP=0) Output R/W Input Output Input(RSTUP=1) P40 Port 4 P41 Input(RSTUP=0) Output CS0 Input(RSTUP=1) Input(RSTUP=0) Output CS1 I/O Register Settings Pn 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 0 1 PnCR 0 1 0 1 0 1 0 1 0 1 PnFC PnFC2 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 Port 3 P37 TMP1942CY/CZ-65 TMP1942CY/CZ Table 3.5.2 I/O Port Programmability (2/4) Port Pin Name Direction / Function Input(RSTUP=1) P42 Input(RSTUP=0) Output CS2 Input(RSTUP=1) Port 4 P43 Input(RSTUP=0) Output CS3 Input P44 Output SCOUT Input Port 5 P50~P57 AN0~AN7 ADTRG Input Port 6 P60~P67 AN8~AN15 KEY0~7 P90~P97 P90 P91 Port 9 P92 P93 P94 P95 P96 P97 PA0~PA7 PA0 PA1 PA2 Port A PA3 PA4 PA5 PA6 PA7 Input Output KEY8 KEY9 TB40UT TB5OUT TB6OUT TB7IN0 TB7IN1 TB7OUT Input Output TB0IN0 INT3 TB0IN1 INT4 TB0OUT TB1IN0 INT5 TB1IN1 INT6 TB1OUT TA1OUT TA0IN KEYA I/O Register Settings Pn 1 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 PnCR 0 0 1 0 0 1 0 1 - PnFC 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 1* 1 1* 1 1 1 1 1 1 1 PnFC2 TMP1942CY/CZ-66 TMP1942CY/CZ Table 3.5.2 I/O Port Programmability (3/4) Port Pin Name PB0~PB7 PB0 PB1 PB2 Port B PB3 PB4 PB5 PB6 PB7 Direction / Function Input Output TB2IN0 INTB TB2IN1 INTC TB2OUT TB4IN0 TB3IN0 INTD TB3IN1 INTE TB3OUT TB4IN1 TA3OUT TA2IN INT7 KEYB Input Output TA4IN INT8 TA6IN INT9 TA8IN INTA TA5OUT TAAIN TA7OUT TB8IN0 KEYC TB8IN1 TA9OUT Input Output TXD0 TB9IN0 RXD0 TB9IN1 SCLK0(Input) SCLK0(Output) CTS0 TXD1 TBAIN0 RXD1 TBAIN1 I/O Register Settings Pn - PnCR 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 0 PnFC 0 0 1 1* 1 1* 1 1 1 1* 1 1* 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 PnFC2 PC0~PC7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0~PD7 PD0 PD1 Port D PD2 Port C - PD3 PD4 TMP1942CY/CZ-67 TMP1942CY/CZ Table 3.5.2 I/O Port Programmability (4/4) Port Pin Name Direction / Function SCLK1(Input) SCLK1(Output) CTS3 TABOUT XT1 XT2 Input Output TXD3 RXD3 SCLK3(Input) SCLK3(Output) CTS3 TXD4 RXD4 SCLK4(Input) SCLK4(Output) CTS4 INT1 INT2 Input Output TXD5 RXD5 KEYD SCLK5(Input) SCLK5(Output) CTS SCK(Input) SCK(Output) SO SDA SI SCL INT0 I/O Register Settings Pn - PnCR 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 1 1 0 PnFC 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1* 1* 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1* PnFC2 0 0 0 1 - PD5 Port D PD6 PD7 PE0~PE7 PE0 PE1 PE2 Port E PE3 PE4 PE5 PE6 PE7 PF0~PF6 PF0 PF1 PF2 Port F PF3 PF4 PF5 PF6 X: Don't care Pn: Port n Register, PnCR: Port n Control Register, PnFC: Port n Function Register *: Set this bit when using the pin for a STOP mode termination interrupt with SYSCR HWR , R / W and P40 to P43 have their internal pullup resistors enabled when the corresponding P4FC register bit is set and when the bus is released. Note 2: When P50-P57 are configured as analog channels of the ADC, the ADCH[2:0] field in A/D Mode Control Register 1 (ADMOD1) is used to select a channel(s). Note 3: When P57 is configured as ADTRG , the ADTRGE bit in the ADMOD1 register is used to enable and disable the external trigger input to the ADC. Note 4: When PD6-PD7 are configured as XT1-XT2, the SYSCR0 register must be programmed to enable oscillation, etc. Note 5: When PortD and PortE and PortF are configured as SDA and SCL outputs for the SBI, the ODEA[7:6] field in the Open-Drain Enable (ODE) register can be used to configure them as either push-pull or open-drain ouptuts. Upon reset, the default is push-pull. TMP1942CY/CZ-68 TMP1942CY/CZ 3.5.1 Port 0 (P00-P07) Port 0 is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. Use the control register P0CR to set the port for input or output. A reset clears all bits of P0CR to 0 and puts port 0 in input mode. In addition to functioning as a general-purpose input/output port, this port can also function as an address/data bus (AD0-AD7). When external memory is accessed, this port automatically functions as an address/data bus (AD0-AD7), with all bits of P0CR cleared to 0. Reset Direction Control (bitwise) STOP DRIVE Write to P0CR Internal Data Bus Output Latch Output Buffer Write to P0 Port 0 P00-P07 (AD0-AD7) Read P0 Figure 0.1 Port 0 (P00-P07) Note: The above system diagram does not represent the address/data bus function. TMP1942CY/CZ-69 TMP1942CY/CZ Port 0 Register 7 P0 (0xFFFF_F000) Bit Symbol Read/Write After Reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Input mode (output latch register cleared to 0) Port 0 Control Register 7 P0CR (0xFFFF_F002) Bit Symbol Read/Write After Reset Function 0 0 0 0 P07C 6 P06C 5 P05C 4 P04C W 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 0: IN 1: OUT (Functions as AD7-AD0 when external area is accessed, with the register cleared to 0.) Input/output setting for port 0 0 1 Input Output Figure 0.2 Registers Related to Port 0 TMP1942CY/CZ-70 TMP1942CY/CZ 3.5.2 Port 1 (P10-P17) Port 1 is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register P1CR and function register P1FC are used to set the port for input or output. A reset clears all bits of output latch P1 and all bits of P1CR and P1FC to 0, putting port 1 in input mode. In addition to functioning as a general-purpose input/output port, this port can also function as an address/data bus (AD8-AD15) or an address bus (A8-A15). To access external memory, set this port to an address bus or address/data bus using P1CR and P1FC. Reset Direction Control (bitwise) Write to P1CR Function Control (bitwise) Internal Data Bus Write to P1FC STOP DRIVE Port 1 P10-P17 (AD8-AD15/A8-A15) Output Latch Output Buffer Write to P1 Read P1 Figure 0.3 Port 1 (P10-P17) Note: The above system diagram does not represent the address/data bus function. TMP1942CY/CZ-71 TMP1942CY/CZ Port 1 Register 7 P1 (0xFFFF_F001) Bit Symbol Read/Write After Reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Input mode (output latch register cleared to 0) Port 1 Control Register 7 P1CR (0xFFFF_F004) Bit Symbol Read/Write After Reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 << Refer to P1FC. >> Port 1 Function Register 7 P1FC (0xFFFF_F005) Bit Symbol Read/Write After Reset Function 0 0 0 0 P17F 6 P16F 5 P15F 4 P14F W 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: IN, 01: OUT, 10: AD15-8, 11: A15-8 Function settings for port 1 P1CR Figure 0.4 Registers Related to Port 1 TMP1942CY/CZ-72 TMP1942CY/CZ 3.5.3 Port 2 (P20-P27) Port 2 is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register P2CR and function register P2FC are used to set the port for input or output. A reset sets all bits of output latch P2 to 1 and clears all bits of P2CR and P2FC to 0, putting port 2 in input mode. In addition to functioning as a general-purpose input/output port, this port can function as an address bus (A0-A7 or A16-A23). A16-23 A0-7 Reset Selector S B A Y Direction Control (bitwise) Write to P2CR Function Control (bitwise) Internal Data Bus STOP DRIVE S B Selector Output Latch A Y Output Buffer Write to P2 Port 2 P20-P27 (A0-A7/A16-A23) Write to P2FC Read P2 Figure 0.5 Port 2 (P20-P27) TMP1942CY/CZ-73 TMP1942CY/CZ Port 2 Control Register 7 P2 (0xFFFF_F012) Bit Symbol Read/Write After Reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Input mode (output latch register set to 1) Port 2 Control Register 7 P2CR (0xFFFF_F014) Bit Symbol Read/Write After Reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 << Refer to P2FC.>> Port 2 Function Register 7 P2FC (0xFFFF_F015) Bit Symbol Read/Write After Reset Function 0 0 0 0 P27F 6 P26F 5 P25F 4 P24F W 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: IN, 01: OUT, 10: A7-0, 11: A23-16 Function settings for port 2 P2CR Figure 0.6 Registers Related to Port 2 TMP1942CY/CZ-74 TMP1942CY/CZ 3.5.4 Port 3 (P30-P37) Port 3 is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output, with the exception that P30 and P31 are output-only. The control register P3CR and function register P3FC are used to set the port for input or output. A reset sets bits P30, P31 and P37 of the output latch to 1. Bits P32 to P36 are set to 1 by a reset if RSTPUP is High or cleared to 0 if RSTPUP is Low. All bits of P3CR (bits 0 and 1 not used) and P3FC (bits 3 and 7 not used) are cleared to 0 by a reset, with P30 and P31 outputting a High signal and P32 to P36 placed in input mode with pull-up resistors enabled (if RSTPUP is High) or disabled (if RSTPUP is Low). P37 is placed in input mode with a pull-up resistor enabled regardless of the value of RSTPUP. In addition to functioning as a general-purpose input/output port, this port can also input and output the CPU's control and status signals. The RD strobe is output only when an external address area is being accessed while the P30 pin is set for RD output ( Reset Function Control (bitwise) Internal Data Bus Write to P3FC Selector S Output Latch S A B P30 ( RD ) P31 ( WR ) Output Buffer Write to P3 RD , WR Read P3 Figure 0.7 Port 3 (P30, P31) TMP1942CY/CZ-75 TMP1942CY/CZ Reset Direction Control (bitwise) Write to P3CR STOP DRIVE Function Control (bitwise) InternalDataBus Write to P3FC RSTPUP S Selector P-ch Programmable Pull-up Resistor S R A Output Latch B Write to P3 Output Buffer P32 ( HWR ) P35 ( BUSAK ) P36 ( R / W ) Reset HWR , BUSAK , R / W Read P3 Figure 0.8 Port 3 (P32, P35, P36) TMP1942CY/CZ-76 TMP1942CY/CZ Reset Direction Control (bitwise) STOP DRIVE Write to P3CR RSTPUP Internal Data Bus P-ch Programmable Pull-up Resistor S R Output Latch Output Buffer Write to P3 Reset P33 ( WAIT ) Internal WAIT Reset Read P3 Direction Control (bitwise) STOP DRIVE Write to P3CR Function Control (bitwise) Write to P3FC Internal Data Bus P-ch RSTPUP Programmable Pull-up Resistor S R Output Latch Output Buffer Write to P3 Reset P34 ( BUSRQ ) Read P3 Internal BUSRQ Figure 0.9 Port 3 (P33, P34) TMP1942CY/CZ-77 TMP1942CY/CZ Reset Direction Control (bitwise) STOP DRIVE Write to P3CR P-ch Internal data bus Programmable Pull-up Resistor S Output Latch Output Buffer Write to P3 P37 ( DSU ) Internal DSU Read P3 Figure 0.10 Port 3 (P37) TMP1942CY/CZ-78 TMP1942CY/CZ Port 3 Register 7 P3 (0xFFFF_F018) Bit Symbol Read/Write After Reset RSTPUP = 0 1 (Pull-UP) 0 0 Input Mode 0 0 0 P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 0 P30 Output Mode 1 1 1 1 RSTPUP = 1 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) 1 (Pull-UP) Port 3 Control Register 7 P3CR (0xFFFF_F01A) Bit Symbol Read/Write After Reset Function 0 0 0 P37C 6 P36C 5 P35C W 4 P34C 0 0: IN 3 P33C 0 1: OUT 2 P32C 0 1 0 Input/output settings for port 3 0 1 Input Output Port 3 Function Register 7 P3FC (0xFFFF_F01B) Bit Symbol Read/Write After Reset Function 6 P36F 0 0: PORT 1: R / W 5 P35F 0 0: PORT 1: BUSAK 4 P34F W 0 0: PORT 1: BUSRQ 3 2 P32F 0 0: PORT 1: HWR 1 P31F 0 0: PORT 1: WR 0 P30F 0 0: PORT 1: RD BUSRQ settings P3FC P30 ( RD ) function settings BUSAK settings P3FC Outputs RD only during external access. Outputs WR WR only during external access. HWR settings P3FC Figure 0.11 Registers Related to Port 3 TMP1942CY/CZ-79 TMP1942CY/CZ 3.5.5 Port 4 (P40-P44) Port 4 is a 5-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register P4CR and function register P4FC are used to set the port for input or output. Bits P41 to P44 of the output latch register are set to 1 by a reset if RSTPUP is High or cleared to 0 if RSTPUP is Low. Bit P44 of the output latch register is set to 1 regardless of the value of RSTPUP. All bits of P4CR and P4FC are cleared to 0 by a reset, with P40 to P43 placed in input mode with pull-up resistors enabled (if RSTPUP is High) or disabled (if RSTPUP is Low). P44 is placed in input mode with a pull-up resistor disabled regardless of the value of RSTPUP. In addition to functioning as a general-purpose input/output port, P40-P43 can also output the chip select signals (CS0-CS3), and P44 functions as the SCOUT pin, outputting the system clock. Reset Direction Control (bitwise) Write to P4CR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to P4FC RSTPUP S A Selector P-ch Programmable Pull-up Resistor S R P40 ( CS0 ) Output Latch Reset P41 ( CS1) P42 ( CS2 ) P43 ( CS3 ) Output Latch B Write to P4 CS0 , CS1, CS2 , CS3 Read P4 Figure 0.12 Port 4 (P40-P43) TMP1942CY/CZ-80 TMP1942CY/CZ Reset R Direction Control (bitwise) STOP DRIVE Write to P4CR R Function Control (bitwise) Internal data bus Write to P4FC S Output Latch AS Selector Y P44 (SCOUT) Reset Write to P4 B S B Y Selector Read P4 fSYS clock fs clock A Selector B S Y A SYSCR3 Figure 0.13 Port 4 (P44) TMP1942CY/CZ-81 TMP1942CY/CZ Port 4 Register 7 P4 (0xFFFF_F01E) Bit Symbol Read/Write After Reset RSTPUP=1 RSTPUP=0 6 5 4 P44 3 P43 2 P42 R/W Input mode 1 P41 0 P40 1 1 1 (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) 1 (Pull-Up) 0 0 0 0 RSTPUp = 1 RSTPUp = 0 Port 4 Control Register 7 P4CR (0xFFFF_F020) Bit Symbol Read/Write After Reset 6 5 4 P44C 0 3 P43C 0 0: IN 2 P42C W 0 1 P41C 0 1: OUT 0 P40C 0 Port 4 Function Register 7 P4FC (0xFFFF_F021) Bit Symbol Read/Write After Reset Function 6 5 4 P44F 0 0: PORT 1: SCOUT 3 P43F 0 2 P42F W 0 0: PORT 1: CS 1 P41F 0 0 P40F 0 0 1 0 1 0 1 0 1 PORT (P40) CS0 PORT (P41) CS1 PORT (P42) CS2 PORT (P43) CS3 Figure 0.14 Registers Related to Port 4 TMP1942CY/CZ-82 TMP1942CY/CZ 3.5.6 Port 5 (P50-P57) Port 5 is an 8-bit input-only port, and is shared with the A/D converter's analog input pins. P57 also functions as the A/D converter's A/D trigger input pin. Internal Data Bus Read Port 5 Port 5 P50-P56 (AN0-AN7) Conversion Result Register Read A/D A/D Converter Channel Selector Function Control Write P5FC Port 5 P57 (AN7)/ ADTRG Internal Data Bus Read Port 5 Conversion Result Register Read A/D A/D Converter Channel Selector ADTRG (P57 Only) Figure 0.15 Port 5 (P50-P57) TMP1942CY/CZ-83 TMP1942CY/CZ Port 5 Register 7 P5 (0xFFFF_F040) Bit Symbol Read/Write After Reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Input mode Port 5 Function Register 7 P5FC (0xFFFF_F043) Bit Symbol Read/Write After Reset Function P57F W 0 0: Port or A/D input 1: ADTRG 6 5 4 3 2 1 0 Figure 0.16 Port 5 (P50-P57) Note 1: Use A/D converter mode register ADMOD4 to select A/D converter input channels and to enable A/D trigger input for P57. Note 2: To use ADTRG , first set TMP1942CY/CZ-84 TMP1942CY/CZ 3.5.7 Port 6 (P60-P67) Port 6 is an 8-bit input-only port, and is shared with the A/D converter's analog input pins and key input pins. A reset clears P6FC to 0, placing port 6 in A/D or port input mode. Writing a 1 to a bit of P6FC enables the corresponding pin to be used as a key input pin. Port 6 has pull-up resistors, which are enabled only for those pins for which KWUPCNT Function Control Write P6FC Port 6 P60-67 (AN8-15)/ KEY0-7 Internal Data Bus Read Port 6 Conversion Result Register Read A/D A/D Converter Channel Selector KEY0-7 DPE A Selector KEYmEN Y PE fs TG B Figure 0.17 Port 6 (P60-P67) Port 6 Register 7 P6 (0xFFFF_F041) Bit Symbol Read/Write After Reset P67 6 P66 5 P65 4 P64 R 3 P63 2 P62 1 P61 0 P60 Input mode Port 6 Function Register 7 P6FC (0xFFFF_F045) Bit Symbol Read/Write After Reset Function P67F 6 P66F 5 P65F 4 P64F W 0 3 P63F 2 P62F 1 P61F 0 P60F 0: Port or A/D input 1: Key input Figure 0.18 Registers Related to Port 6 TMP1942CY/CZ-85 TMP1942CY/CZ 3.5.8 Port 9 (P90-P97) Port 9 is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register P9CR is used to set the port for input or output. A reset clears P9CR to 0, putting port 9 in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: P90 and P91 function as key input, P92 to P94 and P97 as 16-bit timer output, and P95 and P96 as 16-bit timer input. These functions are enabled by setting the corresponding bits of P9FC to 1. A reset clears P9CR and P9FC to 0, placing port 9 in input mode. Pins P90 and P91 have pull-up resistors, which are enabled only for those pins for which KWUPCNT Function Control Reset Write to P9FC Direction Control (bitwise) STOP DRIVE Write to P9CR S Internal Data Bus Output Latch P90 (KEY8) P91 (KEY9) Output Buffer Reset Write to P9 Read P9 KEY8, 9 DPE A Selector KEYmEN Y PE fs TG B Figure 0.19 Port 9 (P90, P91) TMP1942CY/CZ-86 TMP1942CY/CZ Reset Direction Control (bitwise) Write to P9CR Function Control (bitwise) STOP DRIVE Write to P9FC Internal DataBus S Output Latch Write to P9 S Selector Read P9 A B P95 (TB7IN0) P96 (TB7IN1) TB7IN0, 1 Reset Direction Control (bitwise) Write to P9CR Function Control (bitwise) STOP DRIVE Internal Data Bus Write to P9FC S Output Latch A S Selector P92 (TB4OUT) P93 (TB5OUT) P94 (TB6OUT) P97 (TB7OUT) Write to P9 Timer F/F Output TB4OUT: Timer B4 TB5OUT: Timer B5 TB6OUT: Timer B6 TB7OUT: Timer B7 B S Selector B Read P9 A Figure 0.20 Port 9 (P92-P97) TMP1942CY/CZ-87 TMP1942CY/CZ Port 9 Register 7 P9 Bit Symbol (0xFFFF_F04C) Read/Write After Reset P97 6 P96 5 P95 4 P94 R/W 3 P93 2 P92 1 P91 0 P90 Input mode (output latch register set to 1) Port 9 Control Register 7 P9CR (0xFFFF_F04E) Bit Symbol Read/Write After Reset Function 0 0 0 0 0: IN P97C 6 P96C 5 P95C 4 P94C W 3 P93C 0 1: OUT 2 P92C 0 1 P91C 0 0 P90C 0 Input/output settings for port 9 0 1 Input Output Port 9 Function Register 7 P9FC (0xFFFF_F04F) Bit Symbol Read/Write After Reset Function 0 0 0 0: PORT 1: TB7IN0 0 0: PORT 0: PORT 1: TB7OUT 1: TB7IN1 P97F 6 P96F 5 P95F 4 P94F W 3 P93F 0 2 P92F 0 1 P91F 0 0 P90F 0 0: PORT 1: KEY8 0: PORT 0: PORT 0: PORT 0: PORT 1: TB6OUT 1: TB5OUT 1: TB4OUT 1: KEY9 Function Select KEY8 input Select KEY9 input Select TB4OUT output Select TB5OUT output Select TB6OUT output Select TB7IN0 input Select TB7IN1 input Select TB7OUT output Corresponding P9FC Bit 1 1 1 1 1 1 1 1 Corresponding P9CR Bit 0 0 1 1 1 0 0 1 Port Used P90 P91 P92 P93 P94 P95 P96 P97 Figure 0.21 Registers Related to Port 9 TMP1942CY/CZ-88 TMP1942CY/CZ 3.5 3.5.9 Port A (PA0-PA7) Port A is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PACR is used to set the port for input or output. A reset clears PACR to 0, putting port A in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PA0, PA1, PA3 and PA4 function as 16-bit timer input or external interrupt input, PA2 and PA5 as 16-bit timer output, PA6 as 8-bit timer output, and PA7 as 8-bit timer input or key input. These functions are enabled by setting the corresponding bits of PAFC to 1. A reset clears PACR and PAFC to 0, placing port A in input mode. PA7 has a pull-up resistor, which is enabled only when KWUPCNT Reset Direction Control (bitwise) Write to PACR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PAFC S Output Latch A Selector Write to PA Timer F/F Output TB0OUT TB1OUT TA1OUT S B Selector Read PA A B PA2 (TB0OUT) PA5 (TB1OUT) PA6 (TA1OUT) S Figure 3.5.21 Port A (PA2, PA5, PA6) TMP1942CY/CZ-89 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PACR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PAFC S Output Latch PA0 (TB0IN0/INT3) PA1 (TB0IN1/INT4) S Selector Read PA TB0IN0, TB0IN1 INT3, INT4 Reset A Write to PA B Direction Control (bitwise) STOP DRIVE Write to PACR Function Control (bitwise) Internal data bus Write to PAFC S Output Latch PA7 (TA0IN/KEYA) Write to PA S Selector B Reset Read PA TA0IN KEYA DPE Selector A TG A KEYmEN Y PE fs B Figure 3.5.22 Port A (PA0, PA1, PA7) TMP1942CY/CZ-90 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PACR STOP DRIVE Function Control (bitwise) Internal data bus Write to PAFC S Output Latch PA3 (TB1IN0/INT5) PA4 (TB1IN1/INT6) S Selector Read PA TB1IN0, TB1IN1 INT5, INT6 A Write to PA B Figure 3.5.23 Port A (PA3, PA4) TMP1942CY/CZ-91 TMP1942CY/CZ Port A Register 7 PA (0xFFFF_F050) Bit Symbol Read/Write After Reset 1 1 1 1 PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 Input mode (output latch register set to 1) 1 1 1 1 Port A Control Register 7 PACR (0xFFFF_F052) Bit Symbol Read/Write After Reset Function 0 0 0 0: IN 0 1: OUT Input/output settings for port A 0 1 Input Output PA7C 6 PA6C 5 PA5C 4 PA4C W 3 PA3C 0 2 PA2C 0 1 PA1C 0 0 PA0C 0 Port A Function Register 7 PAFC (0xFFFF_F053) Bit Symbol Read/Write After Reset Function 0 0: PORT 1: TA0IN KEYA 0 0: PORT 0 0: PORT 0 0: PORT PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 0 0: PORT 2 PA2F 0 0: PORT 1 PA1F 0 0: PORT 0 PA0F 0 0: PORT 1: TB0IN0 INT3 1: TA1OUT 1: TB1OUT 1: TB1IN1 INT6 1: TB1INT0 1: TB0OUT 1: TB0IN1 INT5 INT4 Function Select TB0IN0 input Select INT3 input Select TB0IN1 input Select INT4 input Select TB0OUT output Select TB1IN0 input Select INT5 input Select TB1IN1 input Select INT6 input Select TB1OUT output Select TA1OUT output Select TA0IN input Select KEYA input Corresponding PAFC Bit 1 1 (*1) 1 1 (*1) 1 1 Need not be set 1 Need not be set 1 1 1 1 Corresponding PACR Bit 0 0 0 0 1 0 0 0 0 1 1 0 0 Port Used PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 (*1) Note: Set this bit when using the pin for a STOP mode termination interrupt with SYSCR TMP1942CY/CZ-92 TMP1942CY/CZ 3.5.10 Port B (PB0-PB7) Port B is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PBCR is used to set the port for input or output. A reset clears PBCR to 0, putting port B in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PB0, PB1, PB3 and PB4 function as 16-bit timer input or external interrupt input, PB2 and PB5 as 16-bit timer input or output, PB7 as 8-bit timer input, interrupt input or key input. These functions are enabled by setting the corresponding bits of PBFC to 1. A reset clears PBCR and PBFC to 0, placing port B in input mode. PB7 has a pull-up resistor, which is enabled only when KWUPCNT Reset Direction Control (bitwise) Write to PBCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PBFC S Output Latch A Selector Write to P7 Timer F/F Output TB2OUT TB3OUT S B Selector Read to P7 TB4IN0 TB4IN1 A B PB2 (TB2OUT/TB4IN0) PB5 (TB3OUT/TB4IN1) S Figure 3.5.25 Port B (PB2, PB5) TMP1942CY/CZ-93 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PBCR STOP DRIVE Function Control (bitwise) Internal data bus Write to PBFC S Output Latch PB0 (TB2IN0/INTB) PB1 (TB2IN1/INTC) PB3 (TB3IN0/INTD) PB4 (TB3IN1/INTE) B Write to PB S Selector Read PB TB2IN0, 1 TB3IN0, 1 INTB, C, D, E A Reset Direction Control (bitwise) Write to PBCR STOP DRIVE Function Control (bitwise) Internal data bus Write to PBFC S Output Latch A Selector Write to PB Timer F/F output (TA3OUT: Timer A3) S B Selector Read PB A B PB6 (TA3OUT) S Figure 3.5.26 Port B (PB0, PB1, PB3, PB4, PB6) TMP1942CY/CZ-94 TMP1942CY/CZ Reset Direction Control (bitwise) STOP DRIVE Write to PBCR Function Control (bitwise) Internal Data Bus Write to PBFC S Output Latch PB7 (TA2IN/INT7/KEYB) Write to PB S Selector B Read PB TA2IN INT7 KEYB DPE Selector A TG B A KEYmEN Y PE fs Figure 3.5.27 Port B (PB7) TMP1942CY/CZ-95 TMP1942CY/CZ Port B Register 7 PB (0xFFFF_F051) Bit Symbol Read/Write After Reset PB7 6 PB6 5 PB5 4 PB4 R/W 3 PB3 2 PB2 1 PB1 0 PB0 Input mode (output latch register set to 1) Port B Control Register 7 PBCR (0xFFFF_F054) Bit Symbol Read/Write After Reset Function 0 0 0 0 0: IN PB7C 6 PB6C 5 PB5C 4 PB4C W 3 PB3C 0 1: OUT 2 PB2C 0 1 PB1C 0 0 PB0C 0 Input/output settings for port B 0 1 Input Output Port B Function Register 7 PBFC (0xFFFF_F055) Bit Symbol Read/Write After Reset Function 0 0:PORT 1:TA2IN INT7 KEYB 0 0: PORT 0 0: PORT 0 0: PORT PB7F 6 PB6F 5 PB5F 4 PB4F W 3 PB3F 0 0: PORT 1: INTD TB3IN0 2 PB2F 0 0: PORT 1 PB1F 0 0: PORT 0 PB0F 0 0: PORT 1: INTB TB2IN0 1: TA3OUT 1: TB3OUT 1: INTE TB4IN1 TB3IN1 1: TB2OUT 1: INTC TB4IN0 TB2IN1 Function Select TB2IN0 input Select INTB input Select TB2IN1 input Select INTC input Select TB2OUT output Select TB4IN0 input Select TB3IN0 input Select INTD input Select TB3IN1 input Select INTE input Select TB3OUT output Select TB4IN1 input Select TA3OUT output Select TA2IN input Select INT7 input Select KEYB input Corresponding PBFC Bit 1 1 (*1) 1 1 (*1) 1 0 1 1 (*1) 1 1 (*1) 1 0 1 1 1 1 Corresponding PBCR Bit 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 Port Used PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 (*1) Note: Set this bit when using the pin for a STOP mode termination interrupt with SYSCR TMP1942CY/CZ-96 TMP1942CY/CZ 3.5.11 Port C (PC0-PC7) Port C is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PCCR is used to set the port for input or output. A reset clears PCCR to 0, putting port C in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PC0, PC1 and PC2 function as 8-bit timer input or external interrupt input, PC3 and PC5 as 8-bit timer output, PC6 as 16-bit timer input or key input, PC4 as 8-bit timer input, and PC7 as 16-bit timer input or 8-bit timer output. These functions are enabled by setting the corresponding bits of PCFC to 1. A reset clears PCCR and PCFC to 0, placing port C in input mode. PC6 has a pull-up resistor, which is enabled only when KWUPCNT Reset Direction Control (bitwise) Write to PCCR STOP DRIVE Function Control (bitwise) Internal data bus Write to PCFC S Output Latch A Selector Write to PC Timer F/F Output TA5OUT TA7OUT S B Selector Read PC A B PC3 (TA5OUT) PC5 (TA7OUT) S Figure 3.5.29 Port C (PC3, PC5) TMP1942CY/CZ-97 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PCCR STOP DRIVE Internal Data Bus Function Control (bitwise) Write to PCFC S Output Latch PC0 (TA4IN/INT8) PC1 (TA6IN/INT9) PC2 (TA8IN/INTA) S Selector Read PC TA4IN, TA6IN TA8IN INT8, 9, A Reset A B Write to PC Direction Control (bitwise) STOP DRIVE Write to PCCR Function Control (bitwise) Internal Data Bus Write to PCFC S Output Latch PC6 (TB8IN0/IN0/KEYC) Reset Write to PC S Selector Read PC TB8IN0 KEYC DPE Selector A TG B KEYmEN Y PE A B fs Figure 3.5.30 Port C (PC0, PC1, PC2, PC6) TMP1942CY/CZ-98 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PCCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PCFC S Output Latch A Selector Write to PC Timer F/F Output TA9OUT S B Selector Read PC TB8IN1 A B PC7 (TB8IN1/TA9OUT) S Reset Direction Control (bitwise) Write to PCCR STOP DRIVE Internal Data Bus Function Control (bitwise) Write to PCFC S Output Latch PC4 (TAIN) Write to PC S Selector B Read PC TAAIN A Figure 3.5.31 Port C (PC7, PC4) TMP1942CY/CZ-99 TMP1942CY/CZ Port C Register 7 PC (0xFFFF_F058) Bit Symbol Read/Write After Reset PC7 6 PC6 5 PC5 4 PC4 R/W 3 PC3 2 PC2 1 PC1 0 PC0 Input mode (output latch register set to 1) Port C Control Register 7 PCCR (0xFFFF_F05A) Bit Symbol Read/Write After Reset Function 0 0 0 PC7C 6 PC6C 5 PC5C 4 PC4C W 0 0: IN 3 PC3C 0 1: OUT 2 PC2C 0 1 PC1C 0 0 PC0C 0 Port C Control Register 0 1 Input Output Port C Function Register 7 PCFC (0xFFFF_F05B) Bit Symbol Read/Write After Reset Function 0 0:PORT 0 0: PORT 0 0: PORT 0 0: PORT PC7F 6 PC6F 5 PC5F 4 PC4F W 3 PC3F 0 0: PORT 2 PC2F 0 0: PORT 1 PC1F 0 0: PORT 1: TA6IN INT9 0 PC0F 0 0: PORT 1: TA4IN INT8 1:TB8IN 1: KEYC TA9OUT TB8IN0 1: TA7OUT 1: TAAIN 1: TA5OUT 1: TA8IN INTA Function Select TA4IN input Select INT8 input Select TA6IN input Select INT9 input Select TA8IN input Select INTA input Select TA5OUT output Select TAAIN input Select TA7OUT output Select TB8IN0 input Select KEYC input Select TB8IN1 input Select TA9OUT output Corresponding PCFC Bit 1 Need not be set 1 Need not be set 1 Need not be set 1 1 1 1 1 1 1 Corresponding PCCR Bit 0 0 0 0 0 0 1 0 1 0 0 0 1 Port Used PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Note: For a pin to which two input functions are assigned in addition to the port function, use the control register for each function module to specify which function is used. Figure 3.5.32 Registers Related to Port C TMP1942CY/CZ-100 TMP1942CY/CZ 3.5.12 Port D (PD0-PD7) Port D is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PDCR is used to set the port for input or output. A reset clears PDCR to 0, putting port D in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PD0 and PD3 function as 16-bit timer input or SIO data output, PD1 and PD4 function as 16-bit timer input or SIO data input, PD2 as SIO serial clock input/output or CTS*input, and PD5 as SIO serial clock input/output, CTS*input, or 16-bit timer output. PD6 and PD7 can be connected to a low-frequency oscillator. These functions are enabled by setting the corresponding bits of PDFC1 to 1. For PD5, however, a combination of PDFC1 and PDFC2 determines whether it is used for a port, SIO, or timer. The output open-drain control register (PDODE) can be used to set PD0, PD2, PD3 and PD5 to open-drain output when they are used for output. PD6 and PD7 are always open-drain output when they are used for output. A reset clears PDCR, PDFC1 and PDFC2 to 0, placing port D in input mode. Reset Direction Control (bitwise) Write to PDCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PDFC S Output Latch S A Selector PD0 (TB9IN0/TXD0) PD3 (TBAIN0/TXD1) Write to PD TXD0 TXD1 B S B Selector Read PD TB9IN0 TBAIN0 A Figure 3.5.33 Port D (PD0, PD3) TMP1942CY/CZ-101 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PDCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PDFC S Output Latch PD1 (RXD0/TB9IN1) PD4 (RXD1/TBAIN1) S Selector Read PD TB9IN1, TBAIN1 RXD0/1 A Write to PD B Reset Direction Control (bitwise) Write to PDCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PDFC S Output Latch A S Selector PD2 (SCLK0/ CTS0 ) Write to PD SCLK Output B Open-drain Setting Possible S Selector B Read PD A CTS0 SCLK0 Figure 3.5.34 Port D (PD1, PD4, PD2) TMP1942CY/CZ-102 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PDCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PDFC S Output Latch S Selector TABOUT Write to PD SCLK1 Output S Selector Read PD CTS1 SCLK1 A B Open-drain Setting Possible PD5 (SCLK1/ CTS1/ TABOUT) Figure 3.5.35 Port D (PD5) Note: The output mode is selected by a combination of PDFC1 and PDFC2. When PDFC1 TMP1942CY/CZ-103 TMP1942CY/CZ Reset S Direction Control (bitwise) Enable Low-frequency Oscillation Write to PDCR S Output Latch Output Buffer (Open-Drain Output) PD6 Internal Data Bus Write to PD S B Y Selector Read PD A (ON with 1) S Direction Control (bitwise) Write to PDCR S Output Latch Output Buffer (Open-drain Output) Low-frequency Clock PD7 Write to PD S B Y Selector Read PD A Figure 3.5.36 Port D (PD6, PD7) TMP1942CY/CZ-104 TMP1942CY/CZ Port D Register 7 PD (0xFFFF_F059) Bit Symbol Read/Write After Reset PD7 6 PD6 5 PD5 4 PD4 R/W 3 PD3 2 PD2 1 PD1 0 PD Input mode (output latch register set to 1) Port D Control Register 7 PDCR Bit Symbol After Reset Function PD7C 1 (0xFFFF_F05C) Read/Write 1 0 0: IN 0 1: OUT Input/output settings for port D 0 1 Input Output 6 PD6C 5 PD5C 4 PD4C W 3 PD3C 0 2 PD2C 0 1 PD1C 0 0 PD0C 0 Port D Function Register 1 7 PDFC1 Bit Symbol After Reset Function 6 5 PD5F 0 0: PORT 1: SCLK1/ CTS1* 4 PD4F W 0 3 PD3F 0 2 PD2F 0 1 PD1F 0 0: PORT 1: TB9IN1 RXD0 0 PD0F 0 0: PORT 1: TB9IN0 TXD0 (0xFFFF_F05D) Read/Write 0: PORT 0: PORT 0: PORT 1: TBAIN1 1: TBAIN0 1: SCLK0/ RXD1 TXD1 CTS0* Port D Function Register 2 7 PDFC2 (0xFFFF_F05E) Bit Symbol Read/Write After Reset Function 6 5 PD5F2 W 0 0: PORT 1: TABOUT 4 3 2 1 0 Port D Open-drain Control Register 7 PDODE (0xFFFF_F05F) Bit Symbol Read/Write After Reset Function 6 5 PDODE5 0 0: CMOS 1: OpenDrain 4 3 PDODE3 W 0 0: CMOS 1: OpenDrain 2 PDODE2 0 0: CMOS 1: OpenDrain 1 0 PDODE0 0 0: CMOS 1: OpenDrain TMP1942CY/CZ-105 TMP1942CY/CZ Corresponding PDFC1 Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Function Select TB9IN0 input Select TXD0 output Select TB9IN1 input Select RXD0 input Select SCLK0 input Select SCLK0 output Select CTS0* input Select TBAIN0 input Select TXD1 output Select TBAIN1 input Select RXD1 input Select SCLK1 input Select SCLK1 output Select CTS1 input Select TABOUT output Corresponding PDFC2 Bit Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) Need not be set (no bit provided) 0 0 0 1 Corresponding PDCR Bit 0 Port Used PD0 1 0 PD1 0 0 1 0 0 PD3 1 0 PD4 0 0 1 0 1 PD5 PD2 Note: For a pin to which two input functions are assigned in addition to the port function, use the control register for each function module to specify which function is used. Figure 3.5.37 Registers Related to Port D TMP1942CY/CZ-106 TMP1942CY/CZ 3.5.13 Port E (PE0-PE7) Port E is an 8-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PECR is used to set the port for input or output. A reset clears PECR to 0, putting port E in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PE0 and PE3 function as SIO data output, PE1 and PE4 as SIO data input, PE2 and PE5 as SIO CLK input/output or CTS* input, and PE6 and PE7 as external interrupt input. These functions are enabled by setting the corresponding bits of PEFC to 1. A reset clears PECR and PEFC to 0, placing port E in input mode. The output open-drain control register (PEODE) can be used to set PE0, PE2, PE3 and PE5 to open-drain output when they are used for output. Reset Direction Control (bitwise) Write to PECR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PEFC S Output Latch A S Selector Write to PE TXD3/4 S Selector Read PE A B B Open-drain Setting Possible PE0 (TXD3) PE1 (TXD4) Figure 3.5.38 Port E (PE0, PE1) TMP1942CY/CZ-107 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PECR STOP DRIVE Internal Data Bus Function Control (bitwise) Write to PEFC S Output Latch PE1 (RXD3) PE4 (RXD4) Write to PE S Selector B Read PE RXD1/4 A Reset Direction Control (bitwise) Write to PECR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PEFC S Output Latch A Write to PE SCLK Output 3 SLK Output 4 S Selector Read PE CTS3*, CTS4* SCLK3, SCLK4 A B S Selector B Open-drain Setting Possible PE2 (SCLK0/ CTS3 ) PE5 (SCLK1/ CTS4 ) Figure 3.5.39 Port E (PE1, PE2, PE4, PE5) TMP1942CY/CZ-108 TMP1942CY/CZ Reset Function Control Direction Control (bitwise) STOP DRIVE Write to PECR Internal Data Bus S Output Latch Output Buffer Write to PE PE6 (INT1) PE7 (INT2) Reset Read PE INT1, 2 Figure 3.5.40 Port E (PE6, PE7) TMP1942CY/CZ-109 TMP1942CY/CZ Port E Register 7 PE (0xFFFF_F060) Bit Symbol Read/Write After Reset PE7 6 PE6 5 PE5 4 PE4 R/W 3 PE3 2 PE2 1 PE1 0 PE0 Input mode (output latch register set to 1) Port E Control Register 7 PECR (0xFFFF_F062) Bit Symbol Read/Write After Reset Function 0 0 0 0 0: IN PE7C 6 PE6C 5 PE5C 4 PE4C W 3 PE3C 0 1: OUT 2 PE2C 0 1 PE1C 0 0 PE0C 0 Input/output settings for port E 0 1 Input Output Port E Function Register 7 PEFC (0xFFFF_F063) Bit Symbol Read/Write After Reset Function 0 0: PORT 1: INT2 0 0: PORT 1: INT1 0 0: PORT 1: SCLK4/ CTS4* 0 0: PORT 1: RXD4 PE7F 6 PE6F 5 PE5F 4 PE4F W 3 PE3F 0 0: PORT 1:ITXD4 2 PE2F 0 0: PORT 1: SCLK3/ CTS3* 1 PE1F 0 0: PORT 1: RXD3 0 PE0F 0 0: PORT 1: TXD3 Port E Open-drain Control Register 7 PEODE (0xFFFF_F066) Bit Symbol Read/Write After Reset Function 6 5 PEODE5 W 0 0: CMOS 1: OpenDrain 4 3 PEODE3 W 0 0: CMOS 1: OpenDrain 2 PEODE2 W 0 0: CMOS 1: OpenDrain 1 0 PEODE0 W 0 0: CMOS 1: OpenDrain Function Select TXD3 output Select RXD3 input Select SCLK3 input Select SCLK3 output Select CTS3 input Select TXD4 output Select RXD4 input Select SCLK4 input Select SCLK4 output Select CTS4 input Select INT1 input Select INT2 input Corresponding PEFC Bit 1 1 1 1 1 1 1 1 1 1 1 (*1) 1 (*1) Corresponding PECR Bit 1 0 0 1 0 1 0 0 1 0 0 0 Port Used PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 *1 Note: Set this bit when using the pin for a STOP mode termination interrupt with SYSCR TMP1942CY/CZ-110 TMP1942CY/CZ 3.5.14 Port F (PF0-PF6) Port F is a 7-bit general-purpose input/output port whose bits can each be set independently for input or output. The control register PFCR is used to set the port for input or output. A reset clears PFCR to 0, putting port F in input mode. In addition to functioning as an input/output port, the pins of this port can also function as various input/output pins: PF0 functions as SIO data output, PF1 as SIO data input or key input, PF2 as SIO CLK input/output or CTS* input, PF3, PF4 and PF5 as SBI input/output, and PF6 as external interrupt input. These functions are enabled by setting the corresponding bits of PFFC to 1. A reset clears PFCR and PFFC to 0, placing port F in input mode. The output open-drain control register (PFODE) can be used to set PF0, PF2, PF4 and PF5 to open-drain output when they are used for output. Port F becomes a 5 V input/output port when 5 V is supplied to its dedicated power supply pin DVCC51. It becomes a VCC-based (3 V) port when VCC is supplied to DVCC51. Reset Direction Control (bitwise) Write to PFCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PFFC S Output Latch A Write to PF TXD5 S Selector Read PF A B S Selector B Open-drain Setting Possible PF0 (TXD5) Figure 3.5.42 Port F (PF0) TMP1942CY/CZ-111 TMP1942CY/CZ Reset Direction Control (bitwise) STOP DRIVE Write to PFCR Internal Data Bus Function Control (bitwise) Write to PFFC S Output Latch PF1 (RXD5/KEYD) Write to PF S Selector B Read PF RXD5 KEYD DPE Selector A A TG KEYmEN Y PE fs B Figure 3.5.43 Port F (PF1) TMP1942CY/CZ-112 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PFCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PFFC S Output Latch A S Selector Write to PF SCLK Output S Selector Read PF CTS5* SCLK5 Reset A B B Open-drain Setting Possible PF2 (CLK5/ CTS5 ) Direction Control (bitwise) Write to PFCR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PFFC S Output Latch A Write to PF SCLK Output S Selector Read PF SCK Input A B S Selector B PF3 (SCK) Reset Figure 3.5.44 Port F (PF2, PF3) TMP1942CY/CZ-113 TMP1942CY/CZ Reset Direction Control (bitwise) Write to PACR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PAFC S Output Latch A Write to PA SO Output S Selector Read PA SDA Input Reset A B S Selector B Open-drain Setting Possible PF4(SO/SDA) Reset Direction Control (bitwise) Write to PACR STOP DRIVE Function Control (bitwise) Internal Data Bus Write to PAFC S Output Latch A Write to PA SO Output S Selector Read PA SI Input SCL Input A B S Selector B Open-drain Setting Possible CDE Figure 3.5.45 Port F (PF4, PF5) TMP1942CY/CZ-114 TMP1942CY/CZ Reset Function Control Direction Control (bitwise) STOP DRIVE Write to PFCR Internal Data Bus S Output Latch Output Buffer Reset Write to PF PF6 (INT0) Read PF INT0 Figure 3.5.46 Port F (PF6) TMP1942CY/CZ-115 TMP1942CY/CZ Port F Register 7 PF (0xFFFF_F061) Bit Symbol Read/Write After Reset 6 PF6 5 PF5 4 PF4 3 PF3 2 PF2 1 PF1 0 PF0 R/W Input mode (output latch register set to 1) Port F Control Register 7 PFCR (0xFFFF_F064) Bit Symbol Read/Write After Reset Function 0 0 0 0 0: IN 6 PF6C 5 PF5C 4 PF4C W 3 PF3C 0 1: OUT 2 PF2C 0 1 PF1C 0 0 PF0C 0 Input/output settings for port F 0 1 Input Output Port F Function Register 7 PEFC (0xFFFF_F065) Bit Symbol Read/Write After Reset Function 6 PF6F W 0 0: PORT 1: INT0 5 PF5F 0 4 PF4F 0 3 PF3F 0 2 PF2F 1 PF1F 0 0: PORT 1: KEYD RXD5 0 PF0F 0 0: PORT 1: TXD5 0 0: PORT 1: SOLK4 COTS5 0: PORT 0: PORT 0: PORT 1: SI/SCIA 1: SO/SDA 1: SOK Port F Open-drain Control Register 7 PEODE (0xFFFF_F067) Bit Symbol Read/Write After Reset Function 6 5 PFODE5 W 0 0: CMOS 1: OpenDrain 4 PFODE4 3 2 PFODE2 W 0 0: CMOS 1: OpenDrain 1 0 PFODE0 W 0 0: CMOS 1: OpenDrain W 0 0: CMOS 1: OpenDrain Function Select TXD5 output Select RXD5 input Select KEYD input Select SCLK4 input Select SCLK4 output Select CTS5 input Select SCK output Select SCK input Select SO/SDA Select SI/SCL Select INT0 input Corresponding PFFC Bit 1 1 1 1 1 1 1 1 1 1 1(*1) Corresponding PFCR Bit 1 0 0 0 1 0 1 0 1 1 0 Port Used PF0 PF1 PF2 PF3 PF4 PF5 PF6 *1 Set this bit when using the pin for a STOP mode termination interrupt with SYSCR Note: TMP1942CY/CZ-116 TMP1942CY/CZ 3.6 External Bus Interface The TMP1942 contains an external bus interface function which is necessary for connecting memory or I/Os which are external to the chip. This function is implemented by the external bus interface circuit (EBIF) and the CS (chip select)/wait controller. The CS/wait controller specifies mapping addresses for any four address spaces, and controls a wait state and data bus width (8 bits or 16 bits) for these four address spaces and other external address spaces. The external bus interface circuit (EBIF) controls timing for the external bus based on settings made with the CS/wait controller. The EBIF also controls dynamic bus sizing and the arbitration of bus contention with external bus masters. * Wait function Can be set individually for each block. * * * * A wait state of up to 7 clock cycles can be automatically inserted. Wait states can be inserted from the WAIT pin. Data bus width The bus width can be independently selected as 8 bits or 16 bits for each block. Read recovery cycle When a external bus cycle is immediately followed by a next external bus cycle, up to two dummy clock cycles can be inserted. Insertion of the dummy cycle(s) can be set individually for each block. * Control of ALE width The ALE width can be set to 0.5 or 1.5 clock cycles. The set ALE width applies to all blocks in common. * Arbitration of bus contention TMP1942CY/CZ-117 TMP1942CY/CZ 3.6.1 Address and data pins (1) Setting address and data pins For external memory connections, port 0 (AD0-AD7), port 1 (AD8-AD15/A8-A15) and port 2 (A16-A23/A0-A7) pins can be used as the address bus and the data bus. One of the following four bus configurations can be selected by setting up the port registers. (1) Number of address bus lines Number of data bus lines Number of multiplexed address/data bus lines Port function Port 0 Port 1 Port 2 max.24 (~16 MB) 8 8 AD0 ~ AD7 A8 ~ A15 A16 ~ A23 (2) max.24 (~16 MB) 16 16 AD0 ~ AD7 AD8 ~ AD15 A16 ~ A23 (3) max.16 (~64 KB) 8 0 AD0 ~ AD7 A8 ~ A15 A0 ~ A7 (4) max.8 (~256 B) 16 0 AD0 ~ AD7 AD8 ~ AD15 A0 ~ A7 A23~8 A23~8 A23~16 A23~16 A15~0 A15~0 (Note1) A7~0 A7~0 (Note1) AD7~0 A7~0 D7~0 AD15~0 A15~0 D15~0 AD7~0 A7~0 D7~0 AD15~0 A15~0 D15~0 Timing diagram ALE ALE ALE ALE RD RD RD RD Note 1: Even for cases (3) and (4), addresses are output because the data bus pins are shared with the address bus. Note 2: Ports 0 to 2 are set for input after a reset, and do not function as address or data bus pins. Note 3: Any one of (1) to (4) can be selected by setting the P1CR, P1FC, P2CR and P2FC registers as desired. (2) Address hold when an internal area is accessed When an internal area is accessed, the address bus retains the previous address which was output by the external area device; thus the address does not change. In addition, the address/data bus is placed in high-impedance state. TMP1942-118 TMP1942CY/CZ 3.6.2 External bus operation This section explains various bus timings. In the following timing diagrams, the address bus is chosen to be A23-A16 and the address/data bus is chosen to be AD15-AD0. (1) Basic bus operation External bus cycles in the TMP1942 essentially consist of three clock cycles. A wait state can be inserted, as will be explained later. The basic clock for external bus cycles is the same as the internal system clock. Figure 3.6.1 shows a read bus timing. Figure 3.6.2 shows a write bus timing. During internal access, the address bus does not change, as shown in the diagram, nor does ALE output a latch pulse. The address/data bus is placed in high-impedance state, and neither RD and WR nor other control signals are asserted. tsys A [23 : 16] AD [15 : 0] ALE ADR DATA Holds upper address Enter Hi-Z state Does not output ALE Does not output RD RD External access Internal access Figure 3.6.1 Read Operation Timing Diagram tsys A [23 : 16] AD [15 : 0] ALE WR Holds upper address Enter Hi-Z state ADR DATA Does not output ALE Does not output WR External area Internal area Figure 3.6.2 Write Operation Timing Diagram Note: fsys expresses one period of share of system clock. TMP1942CY/CZ-119 TMP1942CY/CZ (2) Wait timing Wait cycles can be inserted individually for each block by using the CS/wait controller. The following two types of wait insertion can be used: a. Automatic wait insertion of up to 7 clock cycles b. Wait insertion from WAIT pin Note: "Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width." Timing diagrams with a wait state inserted are shown below. Wait tsys A [23 : 16] Upper address Upper address AD [15 : 0] ALE ADR DATA ADR DATA RD 0 wait 1 wait Figure 3.6.3 Read Operation Timing Diagram (with 0 Wait Cycles and 1 Wait Cycle) Wait tsys A [23 : 16] Upper address Upper address AD [15 : 0] ALE RD ADR DATA ADR DATA WAIT 0 wait (1+ N wait, N = 1) Figure 3.6.4 Read Operation Timing Diagram (1+N Wait Cycles, N = 1) TMP1942-120 TMP1942CY/CZ Wait tsys A [23 : 16] Upper address Upper address AD [15 : 0] ADR DATA ADR DATA ALE WR 0 wait 1 wait Figure 3.6.5 Write Operation Timing Diagram (with 0 Wait Cycles and 1 Wait Cycle) Wait tsys A [23 : 16] Upper address Upper address AD [15 : 0] ADR DATA ADR DATA ALE WR WAIT 0 wait (1+ N wait, N = 1) Figure 3.6.6 Write Operation Timing Diagram (1+N Wait Cycles, N = 1) TMP1942CY/CZ-121 TMP1942CY/CZ (3) ALE assertion time The ALE assertion time can be selected as either 0.5 or 1.5 clock cycles. The bit for setting this assertion time is provided in the system clock control register. The default assertion time is 1.5 clock cycles. The assertion time cannot be set individually for blocks in the external area; it applies universally to the entire external address space. Note: "Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width." tsys ALE (ALESEL = 0) 0.5 clock cycle AD [15 : 0] (ALESEL = 1) 1.5 clock cycles AD [15 : 0] Figure 3.6.7 ALE Assertion Time Figure 3.6.8 shows read operation timing with an ALE assertion time of 0.5 clock cycles and that with an ALE assertion time of 1.5 clock cycles. tsys A [23 : 16] Upper address Upper address AD [15 : 0] ADR DATA ADR DATA ALE RD ALE 0.5 clock cycle ALE 1.5 clock cycles Figure 3.6.8 Read Operation Timing Diagram (with ALE Asserted for 0.5 and 1.5 Clock Cycles) TMP1942-122 TMP1942CY/CZ (4) Read recovery time When an external access occurs after reading from an external area, a dummy cycle can be inserted to create a recovery time. Dummy cycles can only be inserted when the immediately preceding cycle is a read cycle. External read followed by external read: External read followed by external write: Can be inserted Can be inserted External write followed by external access: Cannot be inserted The number of dummy cycles can be specified independently for each block as one clock cycle or two clock cycles. Use the CS/wait controller to set the number of clock cycles. tsys RD AD [15 : 0] Read Data Next ADR ALE AD [15 : 0] Read Data Next ADR ALE Two clock cycles added Figure 3.6.9 Read Recovery Time As shown above, by adding two dummy clock cycles, a sufficient time from the rise of RD to the output of the next address can be secured even when the device is operating at a fast clock speed. Figure 3.6.10 shows a bus timing diagram where one and two dummy clock cycles are inserted. Dummy tsys Upper address Dummy A [23 : 16] AD [15 : 0] DATA ADR DATA ADR ALE RD Dummy cycle (1 clock cycle) Dummy cycles (2 clock cycles) Figure 3.6.10 Read Operation Timing Diagram (with Dummy Cycles Inserted) TMP1942CY/CZ-123 TMP1942CY/CZ 3.6.3 Bus arbitration The TMP1942 allows external bus masters to be connected to the chip. Two signals BUSRQ and BUSAK are used to arbitrate contention for bus control between the processor and external bus masters. External bus masters can only gain control of buses external to the TMP1942. External bus masters cannot gain control of the device's internal bus. (1) Access range for external bus masters External bus masters can only gain control of buses external to the TMP1942. External bus masters cannot gain control of the device's internal bus (G-Bus). Therefore, external bus masters cannot access the device's internal memory and internal I/O blocks. Contention for control of the external bus is arbitrated by the external bus interface circuit (EBIF); hence the CPU and the internal DMAC are not involved in bus arbitration. Even when an external bus master has control of the external bus, the CPU and the internal DMAC can access the internal ROM and RAM and the internal registers. On the other hand, when the CPU or the internal DMAC attempts to access external memory while an external bus master has control of the external bus, the CPU or the internal DMAC is kept waiting until the external bus master finishes control of the external bus. Therefore, if BUSRQ remains asserted for an excessive period of time, the TMP1942 may get locked. (2) Gaining control of the bus An external bus master requests control of the bus from the TMP1942 by asserting the BUSRQ signal. The TMP1942 samples the BUSRQ signal during a break in the external bus cycles on the internal bus (G-Bus) to determine whether or not to grant control of the bus. To give control of the bus to the external bus master, it asserts the BUSAK signal. At the same time, it places the address bus, data bus and bus control signals in high-impedance state. If the data size to be loaded or stored is larger than the width of the bus for the external memory, multiple bus cycles may occur for a single data transfer (bus sizing). In such a case, a break in the external bus cycles will occur when the last bus cycle has finished. The TMP1942 allows the insertion of dummy cycles when external access continues for successive bus cycles. Even in this case it is only when a break in the external bus cycles occurs on the internal bus (G-Bus) that a request for bus control is accepted. During a dummy cycle the next external bus cycle is already activated on the internal bus, so that if the BUSRQ signal is asserted during a dummy cycle, the bus will only be released after the next bus cycle has been completed. Make sure the BUSRQ signal remains asserted until control of the bus has been finished. Figure 3.6.11 shows a timing sequence in which control of the bus is gained by an external bus master. Note: "Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width." TMP1942-124 TMP1942CY/CZ (1) (2) (3) tsys Internal address External address BUSRQ BUSAK TMP1942 external access TMP1942 external access External bus master cycle TMP1942 external access TMP1942 external access (1) BUSRQ is High. (2) The TMP1942 recognizes that BUSRQ has been pulled Low and releases the bus when the bus cycle has been completed. (3) The TMP1942 asserts BUSAK upon completion of the bus cycle. The external bus master recognizes that BUSAK has been asserted Low and gains control of the bus, thereby initiating its bus operation. Figure 3.6.11 Timing at Which Control of the Bus is Gained (3) Relinquishing control of the bus An external bus master relinquishes control of the bus in the following case: * When it no longer requires control of the bus 1) Relinquishing control of the bus when an external bus master no longer requires control of the bus. When the external bus master no longer needs the control of the bus which it gained, it deasserts the BUSRQ signal to return control of the bus to the TMP1942. Figure 3.6.12 shows a timing sequence in which the bus is released because the external bus master no longer requires control of it. (1) (2)(3) tsys Internal address External address BUSRQ BUSAK TMP1942 external access TMP1942 external access External bus master cycle TMP1942 external access TMP1942 external access (1) The external bus master has control of the bus. (2) Because the external bus master no longer requires control of the bus, it deasserts BUSRQ . (3) The TMP1942 recognizes that BUSRQ has reverted to High and responds by deasserting BUSAK . Figure 3.6.12 Timing at Which Control of the Bus is Relinquished TMP1942CY/CZ-125 TMP1942CY/CZ (4) Bus Release Timings tsys Gaddr AD (addr) Internal External 2 External 2 Exter-nal 1 Addr BUSRQ BUSAK External 1 External 2 BUSRQ asserted during internal access (no external wait) Gaddr AD (addr) Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 BUSRQ asserted during internal access (no external wait) Gaddr AD (addr) Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 BUSRQ asserted during internal access (no external wait) Note: Gaddr indicates the address on the G-Bus. AD (addr) indicates the address on the address/data bus. Addr indicates the address on the address bus. TMP1942-126 TMP1942CY/CZ Gaddr AD (addr) External 1 External 1 Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 BUSRQ asserted during external access, followed by internal access (no external wait) Gaddr AD (addr) External 1 External 1 Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 External 3 BUSRQ asserted during external access, followed by internal access (no external wait) Gaddr AD (addr) External 1 External 1 External 2 External 2 External 3 External 3 External 1 Addr BUSRQ BUSAK External 1 External 2 External 3 BUSRQ asserted during external access, followed by external access (no external wait) TMP1942CY/CZ-127 TMP1942CY/CZ Gaddr AD (addr) External 1 External 1a External 1b External 2 External 2 External 1 Addr BUSRQ BUSAK External 1a External 1b External 2 Bus sizing applied (no external wait) Gaddr External 1a External 1 External 1b External 1c External 1d AD (addr) Addr BUSRQ BUSAK External 1a External 1b External 1c External 1d Bus sizing applied (no external wait) TMP1942-128 TMP1942CY/CZ Idle Gaddr AD (addr) External 1 External 1 Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 BUSRQ asserted during external access, followed by internal access (no external wait, 1 idle cycle) Idle Gaddr AD (addr) External 1 External 1 Internal External 2 External 2 External 1 Addr BUSRQ BUSAK External 1 External 2 External 3 BUSRQ asserted during external access, followed by internal access (no external wait, 1 idle cycle) Idle Gaddr AD (addr) External 1 External 1 External 2 External 2 External 3 External 3 External 1 Addr BUSRQ BUSAK External 1 External 2 External 3 BUSRQ asserted during external access, followed by external access (no external wait, 1 idle cycle) TMP1942CY/CZ-129 TMP1942CY/CZ 3.7 Chip Select/Wait Controller The TMP1942 supports direct connections to external devices (I/O devices, ROM and SRAM). The TMP1942 provides four programmable chip select signals. Programmable features include variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back bus cycles. CS0 - CS3 (multiplexed with P40-P43) are the chip select output pins for the CS0-CS3 address ranges. These chip select signals are generated when the CPU or on-chip DMAC issues an address within the programmed ranges. The P40-P43 pins must be configured as CS0-CS3 by programming the Port 4 Control (P4CR) register and the Port 4 Function (P4FC) register. Chip select address ranges are defined in terms of a base address and an address mask. There is a Base/Mask Address (BMAn) register for each of the four chip select signals, where n is a number from 0 to 3. There is also a set of three Chip Select/Wait Control registers, B01CS, B23CS and BEXCS, each of which consists of a master enable bit, a data bus width bit, a wait state field and a dummy cycle field. External memory devices can also use the WAIT pin to insert wait states and consequently prolong read and write bus cycles. 3.7.1 Programming Chip Select Ranges Each of the four chip select address ranges is defined in the BMAn register. The basic chip select model allows one of the chip select output signals ( CS0 - CS3 ) to assert when an address on the address bus falls within a particular programmed range. The B01CS register defines specific operations for CS0 and CS1, and the B23CS register defines specific operations for CS2 and CS3 (see Section 3.7.2). (1) Base/Mask Address Registers The organizations of the BMAn registers are shown in Fig.3.7.1 and Fig. 3.7.2. The base address (BAn) field specifies the starting address for a chip select. Any set bit in the address mask field (MAn) masks the corresponding base address bit. The address mask field determines the block size of a particular chip select line. The address is compared on every bus cycle. /Base address The base address (BAn) field specifies the upper 16 bits (A31-A16) of the starting address for a chip select. The lower 16 bits (A15-A0) are assumed to be zero. Thus, the base address is any multiple of 64 Kbytes starting at 0x0000_0000. Figure 3.7.3 shows the relationships between starting addresses and the BMAn values. /Address mask The address mask (MAn) field defines whether any particular bits of the address should be compared or masked. Any set bit masks the corresponding base address bit. The address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match. Address bits that can be masked (i.e., supported block sizes) differ for the four chip select spaces as follows: CS0 and CS1 spaces: A29-A14 CS2 and CS3 spaces: A30-A15 Note: Use physical addresses in the BMAn registers. TMP1942-130 TMP1942CY/CZ Base/mask address registers BMA0 (0xFFFF_E400) to BMA3 (0xFFFF_E40C) 7 BMA0 (0xFFFF_E400) Bit symbol Read/Write After reset Function 15 Bit symbol Read/Write After reset Function 23 Bit symbol Read/Write After reset Function 31 Bit symbol Read/Write After reset Function 7 BMA1 (0xFFFF_E404) Bit symbol Read/Write After reset Function 15 Bit symbol Read/Write After reset Function 23 Bit symbol Read/Write After reset Function 31 Bit symbol Read/Write After reset Function 0 0 0 0 30 0 0 0 29 0 28 BA1 R/W 0 0 0 0 Sets A31-A24 for the start address. 22 0 0 0 21 0 20 BA1 R/W 0 27 0 26 0 25 0 24 Sets A23-A16 for the start address. 1 1 14 1 13 1 12 MA1 R/W 0 19 0 18 1 17 1 16 Must always be set to 0. 6 5 0 0 0 0 30 0 0 0 29 0 28 BA0 R/W 0 0 0 0 Sets A31-A24 for the start address. 4 MA1 R/W 1 11 1 10 1 9 1 8 Sets the size of the CS1 space. 0: Used for comparing addresses 3 2 1 0 22 0 0 0 21 0 20 BA0 R/W 0 27 0 26 0 25 0 24 Sets A23-A16 for the start address. 1 1 14 1 13 1 12 MA0 R/W 0 19 0 18 1 17 1 16 Must always be set to 0. 6 5 4 MA0 R/W 1 11 1 10 1 9 1 8 Sets the size of the CS0 space. 0: Used for comparing addresses 3 2 1 0 Note: Bits 10-15 in BMA0 and BMA1 must always be set to 0. This is because, although the CS0 and CS1 spaces can have a size of 16 KB to 1 GB, the TMP1942's external address space is limited to 16 MB, which requires setting bits 10-15 to 0 so as not to mask the A24-A29 address bits. Figure 3.7.1 Base/Mask Address Registers (BMA0 and BMA1) TMP1942CY/CZ-131 TMP1942CY/CZ 7 BMA2 (0xFFFF_E408) Bit symbol Read/Write After reset Function 15 Bit symbol Read/Write After reset Function 23 Bit symbol Read/Write After reset Function 31 Bit symbol Read/Write After reset Function 7 BMA3 (0xFFFF_E40C) Bit symbol Read/Write After reset Function 15 Bit symbol Read/Write After reset Function 23 Bit symbol Read/Write After reset Function 31 Bit symbol Read/Write After reset Function 0 0 0 0 30 0 0 0 29 0 28 BA3 R/W 0 0 0 0 Sets A31-A24 for the start address. 22 0 0 0 21 0 20 BA3 R/W 0 27 0 26 0 25 0 24 Sets A23-A16 for the start address. 1 1 14 1 13 1 12 MA3 R/W 0 19 0 18 0 17 1 16 Must always be set to 0. 6 5 0 0 0 0 30 0 0 0 29 0 28 BA2 R/W 0 0 0 0 Sets A31-A24 for the start address. 4 MA3 R/W 1 11 1 10 1 9 1 8 Sets the size of the CS2 space. 0: Used for comparing addresses 3 2 1 0 22 0 0 0 21 0 20 BA2 R/W 0 27 0 26 0 25 0 24 Sets A23-A16 for the start address. 1 1 14 1 13 1 12 MA2 R/W 0 19 0 18 0 17 1 16 Must always be set to 0. 6 5 4 MA2 R/W 1 11 1 10 1 9 1 8 Sets the size of the CS2 space. 0: Used for comparing addresses 3 2 1 0 Note: Bits 9-15 in BMA2 and BMA3 must always be set to 0. This is because, although the CS2 and CS3 spaces can have a size of 32 KB to 2 GB, the TMP1942's external address space is limited to 16 MB, which requires setting bits 9-15 to 0 so as not to mask the A24-A30 address bits. Figure 3.7.2 Base/Mask Address Registers (BMA2 and BMA3) TMP1942-132 TMP1942CY/CZ Address 0xFFFF_FFFF Start address 0xFFFF_0000 Base address value (BAn) FFFF 0x0006_0000 0x0005_0000 0x0004_0000 0x0003_0000 0x0002_0000 0x0001_0000 0x0000_0000 64 Kbytes 0x0000_0000 0006 0005 0004 0003 0002 0001 0000 Figure 3.7.3 Relationship Between Start Address and Base Address Register Values (2) Setting the start address and address space size * Program the BMA0 register as follows to cause CS0 to be asserted in the 64 Kbytes of address space starting at 0xC000_0000. 31 BA0 C 0 0 0 0 0 16 15 MA0 0 3 0 11000000000000000000000000000011 BMA0 Register Value The BA0 field specifies the upper 16 bits of the starting address, or 0xC000. The MA0 field determines whether the A29-A14 bits of the address should be compared or masked. The A31 and A30 bits are always compared. Bits 15-10 of the MA0 field must be cleared so that the A29-A24 bits are always compared. When the BMA0 register is programmed as shown above, the A31-A16 bits of the address are compared to the value of the BA0 field. Consequently, the 64-Kbyte address range between 0xC000_0000 and 0xC000_FFFF is defined as the CS0 space. TMP1942CY/CZ-133 TMP1942CY/CZ * Program the BMA2 register as follows to cause CS2 to be asserted in the 512 Kbyte of address space starting at 0x1FC8_0000. 31 BA2 MA2 00011111110100000000000000011111 1 F D 0 0 0 1 F 16 15 0 BMA2 Register Value The BA2 field specifies the upper 16 bits of the starting address, or 0x1FC8. The MA2 field determines whether the A30-A15 bits of the address should be compared or masked. The A31 bit is always compared. Bits 15-9 of the MA0 field must be cleared so that the A30-A24 bits are always compared. When the BMA2 register is programmed as shown above, the A31-A19 bits of the address are compared to the value of the BA2 field. Consequently, the 1-Mbyte address range between 0x1FC8_0000 and 0x1FCF_FFFF is defined as the CS2 space. Note: The TMP1942 does not assert any CSn signal in the following address ranges: 0xFFFF_8000 through 0x1FFF_BFFF Upon reset, the CS0, CS1 and CS3 spaces are disabled while the CS2 space is enabled and spans the entire 4-GB address space. TMP1942-134 TMP1942CY/CZ (3) Specifying the size of an address space Table 3.7.1 shows the possible sizes of each CS space. If two or more address spaces are specified which overlap one another, the address space with the lowest CS space number will be selected since it has priority. Example: The start address of the CS0 space is 0xC000_0000 and the space size is 16 Kbytes. The start address of the CS1 space is 0xC000_0000 and the space size is 64 Kbytes. CS0 space CS1 space 0xC000_FFFF 0xC000_3FFF 0xC000_0000 0xC000_3FFF 0xC000_0000 When an address within the range of 0xC000_0000 to 0xC000_3FFF is accessed, the CS0 space is selected. Table 3.7.1 CS Spaces and Their Possible Sizes Size (Bytes) CS Space CS0 CS1 CS2 CS3 16 K 32 k 64 K 128 K 256 K 512 K 1M 2M 4M 8M 16 M TMP1942CY/CZ-135 TMP1942CY/CZ 3.7.2 Chip select/wait control registers The chip select/wait control registers are shown in Figure 3.7.4 to Figure 3.7.6. For each address space (i.e., the CS0-CS3 spaces and any other address space), the corresponding chip select/wait control register (B01CS-B23CS or BEXCS) can be used to enable/disable the master, select a chip select output waveform and data bus width, set the number of wait cycles and insert dummy cycles. If two or more address spaces are specified which overlap one another, the address space with the lowest CS space number will be selected since it has priority. (The priority order is CS0 > CS1 > CS2 > CS3 > EXCS.) B01CS (0xFFFF_E480), B23CS (0xFFFF_E484), BEXCS (0xFFFF_E488) 7 B01CS (0xFFFF_E480) 6 B0OM W 0 0 Selects chip select output waveform. 00: ROM/RAM Other settings are not allowed. 5 0 Selects data bus width. 0: 16 bits 1: 8 bits 0 4 B0BUS W 1 0 1 0010: 2 cycles Sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0110: 6 cycles 0111: 7 cycles 1111: (1+N) cycles Other settings are not allowed. 11 B0E W 0 CS0 enable 0: Disable 1: Enable 10 0 9 8 B0RCV 0 Sets the number of dummy cycles to be inserted. (Read recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting not allowed 23 22 B1OM W 0 0 Selects chip select output waveform. 00: ROM/RAM Other settings are not allowed. 21 0 Selects data bus width. 0: 16 bits 1: 8 bits 0 20 B1BUS W 1 0 1 0010: 2 cycles Sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0110: 6 cycles 0111: 7 cycles 1111: (1+N) cycles Other settings are not allowed. 27 B1E W 0 CS1 enable 0: Disable 1: Enable 26 0 25 B1RCV W 0 Sets the number of dummy cycles to be inserted. (Read recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting not allowed 24 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 3 2 B0W 1 0 Bit symbol Read/Write After reset Function 15 14 13 12 Bit symbol Read/Write After reset Function 19 18 B1W 17 16 Bit symbol Read/Write After reset Function 31 30 29 28 Bit symbol Read/Write After reset Function Figure 3.7.4 Chip select/wait control registers Note: "Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width." TMP1942-136 TMP1942CY/CZ 7 B23CS (0xFFFF_E484) Bit symbol Read/Write After reset Function 0 B2OM W 6 5 4 B2BUS 3 2 B2W W 1 0 0 0 Selects data bus width. 0: 16 bits 1: 8 bits 0 1 0 1 0010: 2 cycles Selects chip select output waveform. 00: ROM/RAM Other settings are not allowed. Sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0110: 6 cycles 0111: 7 cycles 1111: (1+N) cycles Other settings are not allowed. 11 B2E 1 CS2 enable 0: Disable 1: Enable 10 B2M W 0 Selects CS2 space. 0 0 Sets the number of dummy cycles to be inserted. 9 B2RCV 8 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 15 Bit symbol Read/Write After reset Function 14 13 12 0: 4-Gbyte (Read recovery time) space 00: 2 cycles 1: CS 01: 1 cycle space 10: None 11: Setting not allowed 18 B3W W 17 16 23 Bit symbol Read/Write After reset Function 0 B3OM W 22 21 20 B3BUS 0 Selects data bus width. 0: 16 bits 1: 8 bits 19 0 0 1 0 1 0010: 2 cycles Selects chip select output waveform. 00: ROM/RAM Other settings are not allowed. Sets the number of wait cycles 0000: 0 cycles 0001: 1 cycle 0110: 6 cycles 0111: 7 cycles 1111: (1+N) cycles Other settings are not allowed. 27 B3E W 0 CS3 enable 0: Disable 1: Enable 26 0 25 B3RCV W 0 Sets the number of dummy cycles to be inserted. (Read recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting not allowed 24 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 31 Bit symbol Read/Write After reset Function 30 29 28 Note: The initial value of B23CS TMP1942CY/CZ-137 TMP1942CY/CZ 7 BEXCS (0xFFFF_E488) Bit symbol Read/Write After reset Function 0 BEXOM W 0 Selects chip select output waveform. 00: ROM/RAM Other settings are not allowed. 15 Bit symbol Read/Write After reset Function 14 13 6 5 0 Selects data bus width. 0: 16 bits 1: 8 bits 12 11 10 0 9 BEXRCV W 0 Sets the number of dummy cycles to be inserted. (Read recovery time) 00: 2 cycles 01: 1 cycle 10: None 11: Setting not allowed 8 0 4 BEXBUS W 1 0 1 Sets the number of wait cycles 0000-0111: 0 cycles to 7 cycles 1111: (1+N) cycles Other settings are not allowed. 3 2 BEXW 1 0 Figure 3.7.6 Chip select/wait control registers Note: "Please set the number of wait as "+1" when you use = long and BUSRQ the ALE width." 3.7.3 Example of Use Figure 3.7.7 shows an example of a TMP1942 system configuration with external memory connected. In this example a 128-Kbyte ROM is connected with a data width of 16 bits and 256-Kbyte RAM is connected with a data width of 16 bits. TMP1942 A16 - 17 AD8 - 15 Latch x 16 A16 A1 - 15 ROM (128 Kbits x 16) A15 A0 - 14 OE CE DQ AD0 - 7 ALE CS2 D8 - 15 D0 - 7 LE RAM (128 Kbits x 8) A16 - 17 A1 - 15 A15 - 16 A0 - 14 OE R/ W I/01 - 8 Upper byte RD HWR CE1 CS1 WR A16 - 17 A1 - 15 RAM (128 Kbits x 8) A15 - 16 A0 - 14 OE I/01 - 8 Lower byte AM1 AM0 R/ W CE1 Figure 3.7.7 Example of External Memory Connection (ROM width = 16 bits, RAM width = 16 bits) When the TMP1942 is reset, the port 4 control register (P4CR) and port 4 function register (P4FC) are both cleared to 0, so that the CS signal output is disabled. To output a CS signal from this port, set the corresponding bits in these registers to 1, first in P4FC and then in P4CR. TMP1942-138 TMP1942CY/CZ 3.8 DMA Controller (DMAC) The TMP1942 incorporates a four-channel DMA controller. 3.8.1 Features The DMAC included in the TMP1942 has the following features: (1) Independent 4-channel DMA (2) Two types of request for control of the bus: with snoop request or without snoop request (3) Transfer request: Internal transfer request: Start by software External transfer request: Request by interrupt (4) Transfer mode: (6) Device size: Dual-address mode 32 bits for memory (16 or 8 bits can also be specified using the CS/wait controller); 8, 16 or 32 bits for I/O (5) Transfer devices: Memory-to-memory, memory-to-I/O, I/O-to-memory (7) Address change: Increment, decrement, fixed, irregular increment or irregular decrement (8) Channel priority: Fixed TMP1942CY/CZ-139 TMP1942CY/CZ 3.8.2 Configuration Internal connections in the TMP1942 3.8.2.1 Figure 3.8.1 shows how the DMAC is connected internally within the TMP1942. INTDREQ [3 : 0]* DACK [3 : 0]* TX19 processor core Interrupt controller External interrupt request Internal I/O interrupt request Indicate bus control relinquished DMAC BUSGNT * Bus control request Request release of bus control Indicate bus control granted Control Address Data BUSREQ * BUSREL * HAVEIT * Note * : internal signal Figure 3.8.1 Internal Connection of DMAC Within the TMP1942 The DMAC has four DMA channels. These channels each receive a data transfer request signal (INTDREQn) from the interrupt controller and return an acknowledge signal ( DACKn ) in response to INTDREQn. The letter `n' denotes the channel number: 0 to 3. Channel 0 has priority over channel 1, channel 1 has priority over channel 2 and channel 2 has priority over channel 3. The TX19 processor core has a snoop function. The snoop function entails the TX19 processor core releasing the core data bus to the DMAC so that the DMAC can access the internal ROM or internal RAM connected to the TX19 processor core. The DMAC can choose whether or not to use the snoop function. For details of the snoop function, refer to Section 3.8.2.3, "Snoop function". There are two types of request for bus control: SREQ and GREQ. The type which is selected depends on whether or not the DMAC is using the snoop function. GREQ is used to request control of the bus when the snoop function is not in use and SREQ is used to request control of the bus when the snoop function is in use. An SREQ bus request has higher priority than a GREQ bus request. Note : DMA channel priority exists only among those using the same type of bus request signal(SREQ or GREQ).For example, once a given DMA channel has acquired bus mastership using SREQ, no other DMA channel can assume bus mastership using GREQ until the ongoing DMA transaction is completed. TMP1942CY/CZ-140 TMP1942CY/CZ 3.8.2.2 Internal blocks of the DMAC Figure 3.8.2 shows the internal blocks of the DMAC. Channel 3 Channel 2 Channel 1 31 Channel 0 31 0 Source Regisuter - 0 Source address register (SAR0) Byte Count Destination - address register (DAR0) Byte count register (BCR0) Status Channel control register (CCR0) Channel status register (CSR0) DMA transfer control register (DTCR0) DMA control register(DCR) Data holding register(DHR) Figure 3.8.2 Internal Blocks of the DMAC 3.8.2.3 Snoop function The TX19 processor core has a snoop function. This function is used to release the TX19 processor core's data bus to the DMAC. When the snoop function is activated, the TX19 processor core releases its data bus to the DMAC. At the same time the TX19 processor core stops operating and remains idle until control of the data bus is returned to it by the DMAC. Since the DMAC can access the processor's internal RAM or internal ROM while the snoop function is active, the RAM or ROM can be specified as the source or destination of a transfer. The TMP1942's internal DMAC can select whether or not to use the TX19 processor core's snoop function. If the DMAC chooses to use the snoop function, it can then access the processor's internal RAM and internal ROM. The CPU in the TX19 processor core will then be stalled until the DMAC cancels the bus request. If the DMAC chooses not to use the snoop function, it cannot access the processor's internal RAM or internal ROM. However, since in this case too the G-Bus is released to the DMAC, if the TX19 processor core attempts to access memory or I/O via the G-Bus and the DMAC does not respond to the request for release of bus control, the TX19 processor core will not be able to execute bus operation, and as a result the pipeline will stall. Note: When the snoop function is not used, the TX19 processor core does not release the data bus to the DMAC. Therefore, if the processor's internal RAM or internal ROM is specified as the source or destination of a DMA transfer, no acknowledge signal will be returned for the DMAC's transfer cycle, resulting in the bus being locked. TMP1942CY/CZ-141 TMP1942CY/CZ 3.8.3 Registers The DMAC incorporates twenty-six 32-bit registers. Table 3.8.1 shows the DMAC register map. Table 3.8.1 DMAC Registers Address 0xFFFF_E200 0xFFFF_E204 0xFFFF_E208 0xFFFF_E20C 0xFFFF_E210 0xFFFF_E218 0xFFFF_E220 0xFFFF_E224 0xFFFF_E228 0xFFFF_E22C 0xFFFF_E230 0xFFFF_E238 0xFFFF_E240 0xFFFF_E244 0xFFFF_E248 0xFFFF_E24C 0xFFFF_E250 0xFFFF_E258 0xFFFF_E260 0xFFFF_E264 0xFFFF_E268 0xFFFF_E26C 0xFFFF_E270 0xFFFF_E278 0xFFFF_E280 0xFFFF_E28C Register Symbol CCR0 CSR0 SAR0 DAR0 BCR0 DTCR0 CCR1 CSR1 SAR1 DAR1 BCR1 DTCR1 CCR2 CSR2 SAR2 DAR2 BCR2 DTCR2 CCR3 CSR3 SAR3 DAR3 BCR3 DTCR3 DCR DHR Register Name Channel control register (ch. 0) Channel status register (ch. 0) Source address register (ch. 0) Destination address register (ch. 0) Byte count register (ch. 0) DMA transfer control register (ch. 0) Channel control register (ch. 1) Channel status register (ch. 1) Source address register (ch. 1) Destination address register (ch. 1) Byte count register (ch. 1) DMA transfer control register (ch. 1) Channel control register (ch. 2) Channel status register (ch. 2) Source address register (ch. 2) Destination address register (ch. 2) Byte count register (ch. 2) DMA transfer control register (ch. 2) Channel control register (ch. 3) Channel status register (ch. 3) Source address register (ch. 3) Destination address register (ch. 3) Byte count register (ch. 3) DMA transfer control register (ch. 3) DMA control register (DMAC) Data-holding register (DMAC) TMP1942CY/CZ-142 TMP1942CY/CZ 3.8.3.1 31 Rst W 0 15 30 DMA control register (DCR) 16 : Type : Initial value 0 : Type : Initial value Bit 31 Mnemonic Rst Field Name Reset Reset (initial value: --) Description Resets the DMAC by software. When the Rst bit is set to 1, all of the DMAC's internal registers are reset to their initial values. Also, all transfer requests are canceled and the four DMA channels are turned off. 0: Don't care 1: Initialize the DMAC. Figure 3.8.3 DMA Control Register (DCR) Note1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in the following sequence: 1. Disable interrupts. 2. Execute NOP four times. 3. Perform a software reset. 4. Perform a software reset again. 5. Re-enable interrupts. Execute steps 3 and 4 consecutively. Note 2: If the software reset command is written to the DCR register immediately after the completion of the last transfer cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software reset only initializes channel registers, etc. Note 3: Don't issue a software reset command to the DCR register via a DMA transfer. TMP1942CY/CZ-143 TMP1942CY/CZ 3.8.3.2 31 Str W 0 15 -- R/W 0 14 ExR R/W 0 13 PosE R/W 0 30 Channel control registers (CCRn) 25 0 24 -- W 23 NIEn R/W 1 7 SAC R/W 00 22 AbIEn R/W 1 6 DIO R/W 0 21 -- R/W 1 5 DAC R/W 00 20 -- R/W 0 4 19 -- R/W 0 3 TrSiz R/W 00 18 -- R/W 0 2 17 Big R/W 1 1 DPS R/W 00 : Type : Initial value 16 -- R/W : Type 0 : Initial value 0 12 Lev R/W 0 11 10 9 SIO R/W 0 8 SReq RelEn R/W 0 R/W 0 Bit 31 Mnemonic Str Field Name Channel Start Start (initial value: --) Description Starts channel operation. When this bit is set to 1, the channel enters ready state. Data transfer can now commence as soon as a transfer request is received. 1 is the only valid value which can be written to this bit; if a 0 is written, it is ignored. When read, this bit always appears to be 0. 1: Start channel operation. 24 23 NIEn (Reserved) Normal Completion Interrupt Enable Abnormal Completion Interrupt Enable (Reserved) (Reserved) (Reserved) (Reserved) Big-Endian This bit is reserved. Make sure that it is always set to 0. Normal Completion Interrupt Enable (initial value: 1) 1: Enable normal completion interrupts. 0: Disable normal completion interrupts. Abnormal Completion Interrupt Enable (initial value 1) 1: Enable abnormal completion interrupts. 0: Disable abnormal completion interrupts. This bit is reserved. Although this bit is initially set to 1, make sure that it is always set to 0. This bit is reserved. Make sure that it is always set to 0. This bit is reserved. Make sure that it is always set to 0. This bit is reserved. Make sure that it is always set to 0. Big-Endian (initial value: 1) 1: The channel operates in big endian mode. 0: The channel operates in little endian mode. On the TMP1942, set this bit to 0. 22 AbIEn 21 20 19 18 17 Big 16 15 14 ExR (Reserved) (Reserved) This bit is reserved. Make sure that it is always set to 0. This bit is reserved. Make sure that it is always set to 0. Specifies the transfer request mode. 1: External transfer request (interrupt-driven start) 0: Internal transfer request (soft start) External Request Mode External Request Mode (initial value: 0) 13 PosE Positive Edge Positive Edge (initial value: 0) Specifies the valid level for the transfer request signal INTDREQn. This specification is effective only when the transfer request is an external transfer request (i.e., when the ExR bit = 1). In the case of internal transfer requests (i.e., when the ExR bit = 0) the value of PosE is ignored. Be sure to set the PosE bit to 0 and the adjacent Lev bit to 1 . Figure 3.8.4 Channel Control Registers (CCRn) (1/2) TMP1942CY/CZ-144 TMP1942CY/CZ Bit 12 Mnemonic Lev Field Name Level Mode Description Level Mode (initial value: 0) Specifies the method for requesting external transfer. This specification is effective only when the transfer request is an external transfer request (i.e., when the ExR bit = 1). In the case of internal transfer requests (i.e., when the ExR bit = 0), the value of Lev is ignored. Be sure to set the Lev bit to 1. 11 SReq Snoop Request Snoop Request (initial value: 0) Specifies whether or not the snoop function is to be used as the bus control request mode. When the function is selected for use, the TX19 processor core's snoop function is activated with the result that the DMAC can use the processor core's data bus. When the function is not selected for use, the TX19 processor core's snoop function remains inactive. 1: The snoop function is used (i.e., the device is in SREQ mode). 0: The snoop function is not used (i.e., the device is in GREQ mode). 10 RelEn Bus Control Release Request Enable Release Request Enable (initial value: 0) Specifies whether the DMAC will respond to requests for release of bus control issued from the TX19 processor core. This function is only effective in GREQ mode. In SREQ mode, this function would have no effect since the TX19 processor core cannot generate a request for release of bus control. 1: After the DMAC has taken over bus control, it will respond to requests for release of bus control. When the TX19 processor core issues a request for release of bus control, the DMAC will return control of the bus to the TX19 processor core when a break in bus operation occurs. 0: The DMAC will not respond to requests for release of bus control. 9 SIO Source I/O Source Type: I/O (initial value: 0) Specifies the source device from which to perform transfer. 1: I/O device 0: Memory 8:7 SAC Source Address Count Source Address Count (initial value: 00) Specifies the way in which the source address changes. 1x: The address is fixed. 01: The address is decremented. 00: The address is incremented. 6 DIO Destination I/O Destination Type: I/O (initial value: 0) Specifies the destination device to which to perform transfer. 1: I/O device 0: Memory 5:4 DAC Destination Address Count Destination Address Count (initial value: 00) Specifies the way in which the destination address changes. 1x: The address is fixed. 01: The address is decremented. 00: The address is incremented. 3:2 TrSiz Transfer Size Transfer Size (initial value: 00) Indicates the amount of data to be transferred in response to one transfer request. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) 1:0 DPS Device Port Size Device Port Size (initial value: 00) Specifies the bus width for the I/O device which has been specified as the source or destination device. 11: 8 bits (1 byte) 10: 16 bits (2 bytes) 0x: 32 bits (4 bytes) Figure 3.8.4 Channel Control Registers (CCRn) (2/2) TMP1942CY/CZ-145 TMP1942CY/CZ 3.8.3.3 31 Act R 0 15 Channel status registers (CSRn) 23 0 NC R/W 0 22 AbC R/W 0 21 -- R/W 0 20 BES R 0 19 BED R 0 3 0 18 Conf R 0 2 -- -- R/W 000 0 ---- : Type : Initial value 00 : Type : Initial value 16 Bit 31 Mnemonic Act Field Name Channel Active Description Channel Active (initial value: 0) Indicates whether the channel is in ready state. 1: Channel is in ready state. 0: Channel is not in ready state. 23 NC Normal Completion Normal Completion (initial value: 0) Indicates whether channel operation has terminated normally. If normal completion interrupts have been enabled by the CCR register, the DMAC generates an interrupt request when this bit is set to 1. The NC bit can be cleared by writing a 0 to it. If a normal completion interrupt has been requested, the interrupt request is dropped when the NC bit is set to 0. If an attempt is made to set the Str bit to 1 while the NC bit = 1, an error results. Be sure to clear the NC bit to 0 before starting the next transfer. Writing a 1 to this bit has no effect. 1: Channel operation has terminated normally. 0: Channel operation has not terminated normally. 22 AbC Abnormal Completion Abnormal Completion (initial value: 0) Indicates whether channel operation has terminated abnormally. If abnormal completion interrupts have been enabled by the CCR register, the DMAC generates an interrupt request when this AbC bit is set to 1. The AbC bit can be cleared by writing a 0 to it. If an abnormal completion interrupt has been requested, the interrupt request is cancelled when the AbC bit is set to 0. When the AbC bit is cleared, the BES, BED and Conf bits are also cleared to 0. If an attempt is made to set the Str bit to 1 while the AbC bit = 1, an error results. Be sure to clear the AbC bit to 0 before starting the next transfer. Writing a 1 to this bit has no effect. 1: Channel operation has terminated abnormally. 0: Channel operation has not terminated abnormally. 21 20 BES (Reserved) Source Bus Error This bit is reserved. Make sure that it is always set to 0. Source Bus Error (initial value: 0) 1: A bus error has occurred while the source was being accessed. 0: No bus error has occurred while the source was being accessed. 19 BED Destination Bus Error Destination Bus Error (initial value: 0) 1: A bus error has occurred while destination was being accessed. 0: No bus error has occurred while destination was being accessed. 18 Conf Configuration Error Configuration Error (initial value: 0) 1: A configuration error has occurred. 0: No configuration error has occurred. 2:0 (Reserved) These three bits are all reserved. Always set all of these bits to 0. Figure 3.8.5 Channel Status Registers (CSRn) TMP1942CY/CZ-146 TMP1942CY/CZ 3.8.3.4 31 SAddr R/W -- 15 SAddr R/W -- : Type : Initial value 0 : Type : Initial value Source address registers (SARn) 16 Bit 31:0 Mnemonic SAddr Field Name Source Address Description Source Address (initial value: --) Sets the physical source address from which data will be transferred. After each transfer the address will change by the value specified in the DPS bits of the CCRn register. Figure 3.8.6 Source Address Registers (SARn) 3.8.3.5 31 Destination address registers (DARn) 16 DAddr R/W -- : Type : Initial value 0 DAddr R/W -- : Type : Initial value 15 Bit 31:0 Mnemonic DAddr Field Name Destination Address Description Destination Address (initial value: --) Sets the physical destination address to which data will be transferred. After each transfer the address will change by the value specified in the DPS bits of the CCRn register. Figure 3.8.7 Destination Address Registers (DARn) TMP1942CY/CZ-147 TMP1942CY/CZ 3.8.3.6 31 0 Byte count registers (BCRn) 24 23 BC R/W -- : Type : Initial value 0 BC R/W -- : Type : Initial value 16 15 Bit 23:0 Mnemonic BC Field Name Byte count Description Byte Count (initial value: --) Sets the number of bytes of data to be transferred. The amount by which the byte count is decremented after each transfer depends on the value specified in the TrSiz bits of the CCRn register. Figure 3.8.8 Byte Count Registers (BCRn) 3.8.3.7 31 DMA transfer control registers (DTCRn) 24 0 : Type : Initial value 23 16 15 0 5 DACM R/W 000 3 2 SACM 0 000 : Type : Initial value Bit 5:3 Mnemonic DACM Field Name Destination Address Count Mode Description Destination Address Count Mode Specifies the mode used for counting the destination address. 000: Count the address beginning at bit 0 of the address counter. 001: Count the address beginning at bit 4 of the address counter. 010: Count the address beginning at bit 8 of the address counter. 011: Count the address beginning at bit 12 of the address counter. 100: Count the address beginning at bit 16 of the address counter. 101: Reserved 110: Reserved 111: Reserved 2:0 SACM Source Address Count Mode Source Address Count Mode Specifies the mode used for counting the source address. 000: Count the address beginning at bit 0 of the address counter. 001: Count the address beginning at bit 4 of the address counter. 010: Count the address beginning at bit 8 of the address counter. 011: Count the address beginning at bit 12 of the address counter. 100: Count the address beginning at bit 16 of the address counter. 101: Reserved 110: Reserved 111: Reserved Figure 3.8.9 DMA Transfer Control Registers (DTCRn) TMP1942CY/CZ-148 TMP1942CY/CZ 3.8.3.8 31 DOT R/W -- 15 DOT R/W -- : Type : Initial value 0 : Type : Initial value Data-holding register (DHR) 16 Bit 31 : 0 Mnemonic DOT Field Name Data on Transfer Description Data on Transfer (initial value: --) This is the data read from the source during a transfer in dual-address mode. Figure 3.8.10 Data-Holding Register (DHR) TMP1942CY/CZ-149 TMP1942CY/CZ 3.8.4 Functions This section describes the functions of the DMAC. 3.8.4.1 Outline The DMAC is a 32-bit DMA controller capable of performing high-speed data transfers in a system incorporating the TX19 processor core without the need for any intervention by the TX19 processor core itself. (1) Source and destination The DMAC performs data transfers between one memory device and another or between a memory device and an I/O device. The device from which data is transferred is referred to as the source device and the device to which data is transferred is referred to as the destination device. Both memory devices and I/O devices can be specified as the source and destination devices. However, the DMAC can only transfer data from a memory device to an I/O device, from an I/O device to memory, or from memory to memory; it cannot transfer data between two I/O devices. The difference between memory devices and I/O devices resides in the methods by which the devices are accessed. When the DMAC accesses an I/O device, it asserts the DACKn signal. Because only one DACKn signal line is available for each channel, the DMAC can only perform one data transfer involving an I/O device at a time; hence the DMAC cannot transfer data from one I/O device to another. An interrupt source can be specified for transfer requests to the DMAC. When an interrupt occurs, the interrupt controller generates a request to the DMAC. (In this case, no interrupt request to the TX19 processor core is generated. For details, refer to Section 3.4, "Interrupts".) This interrupt request from the interrupt controller is canceled by the DACKn signal. Therefore, when an I/O device has been set as a transfer device, a request to the DMAC is cancelled for each transfer performed (i.e., each time the amount of data specified by the TrSiz bits is transferred). On the other hand, in memory-to-memory transfers, DACKn is asserted only when the number of bytes to be transferred (as specified by the value of the BCRn register) falls to 0; hence several data transfers can be performed successively by a single transfer request. For example, when the DMAC is transferring data between the TMP1942's internal I/O and internal (or external) memory, although a transfer request from the internal I/O to the DMAC is cancelled for each transfer performed, the DMAC is kept waiting for the next transfer request unless the number of bytes to be transferred (as specified by the value of the BCRn register) falls to 0. Consequently, DMA transfer is performed successively until the BCRn register value is reduced to 0. TMP1942CY/CZ-150 TMP1942CY/CZ (2) Switching control of the bus (bus arbitration) When a transfer request is issued by the DMAC's internal circuitry, the DMAC requests control of the bus from the TX19 processor core. If an acknowledge signal is returned by the TX19 processor core, the DMAC gains control of the bus and can perform data transfer bus cycles. The DMAC can request two types of bus control: either bus control plus the use of the TX19 processor core's data bus (i.e., the snoop function), or bus control without the snoop function. This can be set independently for each channel in the corresponding register. The TX19 processor core may request release of bus control from the DMAC. Whether the DMAC should respond to this request is set using independent register settings for each channel. However, this response function is effective only when the DMAC does not request the snoop function (i.e., in GREQ mode). When the snoop function is requested (i.e., in SREQ mode), the response function will have no effect because the TX19 processor core cannot generate requests for release of bus control in this mode. When there are no more transfer requests, the DMAC will finish control of the bus. Note1: The NMI interrupt is left pending while the DMAC has control of the bus. Note2: Do not place the TMP1962 in Halt power-down mode while the DMAC is operating. (3) Transfer request modes The DMAC has two transfer request modes: internal transfer request mode and external transfer request mode. In internal transfer request mode, transfer requests are generated internally in the DMAC. A transfer request is generated by setting the start bit in one of the DMAC' internal registers (the s channel control register's Str bit) to 1, upon which the DMAC will start a transfer operation. In external transfer request mode, transfer requests are generated by assertion of the transfer request signal (INTDREQn), which is output by the interrupt controller after the start bit has been set to 1. The DMAC can select level mode, in which a transfer request is generated on detection of a High- or Low-level INTDREQn signal, or edge mode, in which a transfer request is generated on detection of the rising or falling edge of the INTDREQn signal. However, because the INTDREQn signal in the TMP1942 is low-active, always make sure that the transfer request signal is set to be detected at Low level. (4) Address modes Dual-address mode is the only address mode available for the DMAC in the TMP1942. There is no single-address mode for the DMAC. In dual-address mode, data transfers are performed between two memory devices or between memory and an I/O device. The addresses of the source and destination devices are output by the DMAC. When accessing an I/O device, the DMAC asserts the DACKn signal. In dual-address mode, the DMAC executes two bus operations, one for reading and one for writing. The transfer data read from the source device is temporarily stored in the DMAC's internal data-holding register (DHR) before being written to the destination device. TMP1942CY/CZ-151 TMP1942CY/CZ (5) Channel operation The DMAC has four channels (channels 0 to 3). Each channel is activated by setting the start bit (Str) in the channel control register (CCRn) to 1, so that the device enters ready state. When a transfer request occurs while a channel is in ready state, the DMAC gains control of the bus and performs a data transfer. When there are no more transfer requests, the DMAC finishes control of the bus, thereby entering ready state. When transfer for a channel is completed, the channel is placed in idle state. Transfers may be terminated either normally or abnormally (for example, when an error occurs during transfer). An interrupt signal can be generated on completion of transfer. Figure 3.8.11 is a state transition diagram for channel operations. Bus control not owned by DMAC Ready Start Bus control not owned by DMAC Stop Bus control owned by DMAC Transfer completed Transfer Bus control owned by DMAC Figure 3.8.11 State Transitions for Channel Operations (6) Summary of transfer mode combinations The DMAC can perform data transfers as follows according to the combination of mode settings. Transfer Request Internal External Edge/Level Low-level Address Mode Dual Dual Transfer Devices Memory-to-memory Memory-to-memory Memory-to-I/O I/O-to-memory TMP1942CY/CZ-152 TMP1942CY/CZ (7) Address change There are essentially three methods for changing the transfer address: increment, decrement or fixed. The method can be set independently for the source and destination addresses using the SAC and DAC bits in the CCRn register. If the transfer device is a memory device, increment, decrement or fixed may be specified. If the transfer device is an I/O device, only fixed may be specified. When an I/O device is selected as the source or destination device, be sure to set the SAC and DAC bits in the CCRn register to "fixed". If "increment" or "decrement" is selected as the address change method, the bit position at which counting begins can be set using the SACM and DACM bits in the DTCRn register. SACM corresponds to the source address and DACM the destination address. The bit position at which counting the address begins can be specified as bit 0, 4, 8, 12 or 16. Selecting bit 0 results in normal increment or decrement, increment or irregular decrement. Examples of how the address changes are shown below. Example 1: When regular increment is selected for the source device and irregular increment is selected for the destination device SAC: DAC: TrSiz: Source address: SACM = 000: DACM = 001: Increment the address Increment the address Transfer in units of 32 bits 0xA000_1000 Count the address beginning at bit 0 of the address counter Count the address beginning at bit 4 of the address counter Source First time Second time Third time Fourth time 0xA000_1000 0xA000_1004 0xA000_1008 0xA000_100C Destination 0xB000_0000 0xB000_0010 0xB000_0020 0xB000_0030 Destination address: 0xB000_0000 Example 2: When irregular decrement is selected for the source device and regular decrement is selected for the destination device SAC: DAC: TrSiz: Source address: SACM = 010: DACM = 000: Decrement the address Decrement the address Transfer in units of 16 bits Initial value 0xA000_1000 Count the address beginning at bit 8 of the address counter Count the address beginning at bit 0 of the address counter Source First time Second time Third time Fourth time 0xA000_1000 0x9FFF_FF00 0x9FFF_FE00 0x9FFF_FD00 Destination 0xB000_0000 0xAFFF_FFFE 0xAFFF_FFFC 0xAFFF_FFFA Destination address: 0xB000_0000 TMP1942CY/CZ-153 TMP1942CY/CZ 3.8.4.2 Transfer requests For data to be transferred by the DMAC, a transfer request must be generated and transmitted to the DMAC. There are two types of DMAC transfer requests: internal transfer requests and external transfer requests. The transfer request type can be set individually for each channel. For either type of transfer request, when a transfer request occurs after channel operation has been activated, the DMAC will gain control of the bus and perform data transfer. * Internal transfer requests A transfer request can be generated immediately by setting the Str bit in the CCRn register to 1 while the ExR bit in the same register = 0. This transfer request is referred to as an internal transfer request. In the case of an internal transfer request, because the transfer request remains active until channel operation has been completed, data transfers will be performed successively unless transition to a higher priority channel occurs or until bus control is transferred to a higher priority bus master. Internal transfer requests can only be used for transfers between memory and memory. * External transfer requests A transfer request is generated when the interrupt controller is notified of a transfer request by the assertion of the INTDREQn signal for a channel after the channel has been placed in ready state by setting the Str bit of the CCRn register to 1 while the ExR bit in the CCRn register = 0. This transfer request is referred to as an external transfer request. External transfer requests can be used for transfers between two memory devices and between memory and an I/O device. Assertion of the INTDREQn signal is recognized by detecting an edge or a level. The active edge or level is specified using the PosE bit in the CCRn register. However, because the INTDREQn signal in the TMP1942 is low-active, always make sure that the signal is set to be detected at Low level. The amount of data to be transferred for one transfer request is specified using the TrSiz field in the CCRn register. This can be specified as 32 bits, 16 bits or 8 bits. Transfer requests from the interrupt controller are cleared by assertion of the DACKn signal. The DACKn signal is asserted only when the number of bytes to be transferred during an I/O device bus cycle or a memory-to-memory transfer (as specified by the value of the BCRn register) falls to 0. Consequently, for data transfer between memory and an I/O device INTDREQn is cancelled every transfer request with the result that only one transfer is performed for the amount of data specified by TrSiz. On the other hand, in memory-to-memory transfers, INTDREQn is not cancelled until the number of bytes to be transferred (as specified by the value of the BCRn register) falls to 0; hence several data transfers can be performed successively by a single transfer request. Note that if an interrupt of the type specified for INTDREQn is acknowledged by the DMAC, but the interrupt is cleared by the interrupt controller or by another device before the DMAC starts the DMA transfer, one DMA transfer may be performed after the interrupt has been cleared. TMP1942CY/CZ-154 TMP1942CY/CZ 3.8.4.3 Address modes The TMP1942 only supports dual-address mode in which both the source and destination devices are explicitly addressed.. In dual-address mode the DMAC first executes a read from the source device. The data read from the source device is temporarily stored in the DMAC's internal register DHR. Next, the DMAC executes a write to the destination device to write this data to the destination device, thus performing a data transfer from the source to the destination device. Although bit 15 of the CCRn register in the TMP1942 can be used to specify the address mode, this bit must always be set to 0 because the TMP1942 only supports dual-address mode. DMAC Source device Address Address bus Data Data bus (1) (2) (1) (2) Destination device Figure 3.8.12 Diagram of Data Transfer in Dual-Address Mode TMP1942CY/CZ-155 TMP1942CY/CZ DACK DMAC Source device (I/O) Data Address Address bus Data bus Destination device (memory) Figure 3.8.13 Diagram of Data Transfer in Single-Address Mode * Dual-address mode In dual-address mode, a data transfer is executed using two bus operations: -Read operation, in which the DMAC outputs the address of the source device, reads data from the source device and stores the data in its internal register DHR -Write operation, in which the DMAC outputs the address of the destination device and writes the stored data from DHR to the destination device In dual-address mode, three types of transfers can be performed: -Memory-to-memory -Memory-to-I/O device -I/O device-to-memory The units of data transfer performed by the DMAC are equal to the amount of data (32 bits, 16 bits or 8 bits) specified in the TrSiz field of the CCRn register. This amount of data is transferred each time a transfer request is recognized. In dual-address mode, an amount of data equal to the transfer unit is read from the source device into the DHR register, then the data is written from the DHR register to the destination device. Memory accesses occur at intervals equal to the unit of data transfer which has been set. When external memory is accessed, if the transfer unit is 32 bits and the bus width set by the CS/wait controller is 16 bits, then two 16-bit accesses will occur. Similarly, if the transfer unit is 32 bits and the bus width set by the CS/wait controller is 8 bits, then four 8-bit accesses will occur. TMP1942CY/CZ-156 TMP1942CY/CZ For memory-to-I/O device or I/O device-to-memory data transfers, the bus width of the I/O device (the device port size) needs to be set (to 32 bits, 16 bits or 8 bits) using the DPS field in the CCRn register, in addition to the unit of data transfer. If the unit of data transfer and the device port size are equal, the DMAC will perform one read or write operation for the I/O device. If the device port size is smaller than the unit of data transfer, the DMAC will perform multiple read or write operations for the I/O device. For example, when performing a transfer to memory from an I/O device whose device port size is 8 bits when the unit of data transfer is 32 bits, the DMAC will read data from the I/O device and store it in the DHR register four times, 8 bits at a time, and then write 32 bits of data from the DHR register to memory in one operation (or in two operations if the external memory's data bus is 16 bits wide). The source and destination addresses change at intervals equal to the unit of data transfer. The value of the BCRn register also changes by an amount equal to the unit of data transfer. The device port size cannot be set to a value greater than the unit of data transfer. Table 3.8.2 summarizes the above information: Table 3.8.2 Unit of Data Transfer and Device Port Size (Dual-Address Mode) TrSiz 0x (32 bits) 0x (32 bits) 0x (32 bits) 10 (16 bits) 10 (16 bits) 10 (16 bits) 11 (8 bits) 11 (8 bits) 11 (8 bits) DPS 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) 0x (32 bits) 10 (16 bits) 11 (8 bits) Number of Bus Operations Performed on I/O Device Once Twice Four times Setting prohibited Once Twice Setting prohibited Setting prohibited Once Note: The DMAC does not incremnt or decrement the address for I/O peripherals. Therefore, if, for example, TrSiz is programmed to 16 bits and DPS is programmed to 8 bits, both the first and second bus cycles access the lower eight bits of the I/O data bus. TMP1942CY/CZ-157 TMP1942CY/CZ 3.8.4.4 Channel operations A channel is activated when the Str bit in the CCRn register for the channel is set to 1. When a channel is activated, it is checked for errors; if no error is found, it is placed in ready state. If a transfer request occurs while a channel is in ready state, the DMAC gains control of the bus and starts a transfer operation. Channel operation may terminate normally or abnormally, for example, when operation is forcibly terminated or terminated by an error. This status is indicated by the CSRn register. (1) Starting channel operation A channel is activated when the Str bit in the CCRn register for the channel is set to 1. When a channel is activated, it is checked for a configuration error; if no error is found, it is placed in ready state. If an error is detected, the channel operation terminates abnormally. When a channel is placed in ready state, the Act bit in the CSRn register for the channel is set to 1. If internal transfer requests have been set for the channel, a transfer request will be generated immediately, upon which the DMAC will gain control of the bus and start a data transfer. If external transfer requests have been set for the channel, a transfer request will be generated by assertion of INTDREQn, upon which the DMAC will gain control of the bus and start a data transfer. (2) Terminating channel operation Channel operation may terminate either normally or abnormally. This status is indicated in the CSRn register. If an attempt is made to set the Str bit in the CCRn register to 1 while the NC bit or AbC bit of the CSRn register = 1, channel operation will not start and will terminate abnormally. Normal termination Channel operation terminates normally in the following case. Note that, in this case, transfer will always terminate after the DMAC has finished transferring an amount of data equal to the unit of data transfer (the value set in the TrSiz field of the CCRn register). * When data transfer has been completed after the value of the BCRn register has fallen to 0 Abnormal termination Data transfers by the DMAC may terminate abnormally in the following cases: * Termination due to configuration errors A configuration error is an error in the DMA transfer settings. Since a configuration error occurs before the DMAC starts data transfer operation, the SARn, DARn and BCRn register values will remain as set. When operation for a channel terminates abnormally due to a configuration error, the Conf bit in the CSRn register is set to 1 at the same time that the AbC bit is set to 1. Causes of configuration errors are shown below. -Both SIO and DIO are set to 1. -The CCRn Str bit is set to 1 when the NC bit or AbC bit in the CSRn register = 1. TMP1942CY/CZ-158 TMP1942CY/CZ -A value which cannot be divided by the unit of data transfer is set in the BCRn register. -Values which cannot be divided by the unit of data transfer are set in the SARn and DARn registers. -An illegal combination of the device port size and data transfer unit has been set. -The Str bit in the CCRn register is set to 1 while the BCRn register = 0. * Termination due to bus errors When transfer terminates abnormally due to a bus error, the BES or BED bit in the CSRn register is set to 1 at the same time that the AbC bit in the CSRn register is set to 1. -The CPU is notified that a bus error has occurred during data transfer. 3.8.4.5 Channel priority The DMAC has four channels. A channel with a lower channel number always has higher priority. Therefore, if transfer requests occur for channels 0 and 1 simultaneously, the DMAC will perform the transfer operation for channel 0' transfer request first. When there are no more transfer requests s for channel 0, if the transfer request for channel 1 is still in effect, the DMAC will perform the transfer operation on channel 1. (For internal transfer requests, the transfer request is held unless it is cleared. For external transfer requests, this depends on the active state which has been set for the interrupt request assigned to DMA requests by the interrupt controller. If the active state is set to edge mode, the transfer request will be held by the interrupt controller. However, if the active state is set to level mode, the interrupt controller will not hold the transfer request. Therefore, if level mode is set, the interrupt request signal must be kept asserted until it is recognized by the DMAC.) If a transfer request for channel 0 occurs while data transfer on channel 1 is under way, a channel transition will occur. The data transfer on channel 1 will be suspended and the DMAC will start transfer on channel 0. When there are no more transfer request for channel 0, the DMAC will resumes the transfer operation on channel 1. Channel transition occurs when the DMAC has finished transferring an amount of data equal to the unit of data transfer. In dual-address mode, this is when the DMAC has finished writing all the stored data from the DHR register to the destination device. 3.8.4.6 Interrupts The DMAC can generate an interrupt request to the TX19 processor core on completion of channel operation. There are two types of interrupts which can be requested in this case: normal completion interrupt and abnormal completion interrupt. * Normal completion interrupt When channel operation terminates normally, the NC bit in the CSRn register is set to 1. At this time, if normal completion interrupts have been enabled using the NIEn bit in the CCRn register, an interrupt request to the TX19 processor core is generated. * Abnormal completion interrupt When channel operation terminates abnormally, the AbC bit in the CSRn register is set to 1. At this time, if abnormal completion interrupts have been enabled by the AbIEn bit in the CCRn register, an interrupt request to the TX19 processor core is generated. TMP1942CY/CZ-159 TMP1942CY/CZ 3.8.4.7 Endian mode If the unit of data transfer and the device port size are not equal in dual-address mode, the DMAC will assemble or disassemble data in the DHR register. For example, if the source device is an I/O device whose port size is 8 bits while the destination device is a memory device, and the unit of data transfer is 32 bits, the DMAC reads data from the I/O device four times and assembles it into 32 bits of data in the DHR register before writing it to memory. For example, the diagram below shows the relationship between an 8-bit I/O device and a 32-bit DHR register. The TMP1942 supports only little-endian data alignment. I/O device 8 4n + 3 4n + 2 4n + 1 4n + 0 D C B A 0 DHR 31 Big endian 31 Little endian D C B A A B C D 0 0 Figure 3.8.14 Data Packing and Unpacking TMP1942CY/CZ-160 TMP1942CY/CZ 3.8.5 Operation DMAC operations are synchronized to the rising edges of SYSCLK. 3.8.5.1 Dual-address mode * Memory-to-memory transfer Figure 3.8.15 shows a timing example for one transfer session when 16-bit data is being transferred from external memory (which is 16 bits wide) to external memory (which is also 16 bits wide). Although it is not shown here, data is transferred successively until the value of the BCRn register falls to 0. tsys A [23 : 16] CS0 CS1 RD WR / WHR AD [15 : 0] Addr Data Addr Data Read Write Figure 3.8.15 Dual-Address Mode (Memory to Memory) * Memory-to-I/O device transfer Figure 3.8.16 shows a timing example for memory-to-I/O device transfer for cases where the unit of data transfer and the device port size are set to 16 bits and 8 bits, respectively. tsys A [23 : 16] CS0 CS1 RD WR AD [15 : 0] Addr Data Addr Data Addr Data Read Write Write Figure 3.8.16 Dual-Address Mode (Memory to I/O Device) TMP1942CY/CZ-161 TMP1942CY/CZ * I/O device-to-memory transfer Figure 3.8.17 shows a timing example for I/O device-to-memory transfer for cases where the unit of data transfer and the device port size are set to 16 bits and 8 bits, respectively. tsys A [23 : 16] CS0 CS1 RD WR / WHR AD [15 : 0] Addr Data Addr Data Addr Data Read Read Write Figure 3.8.17 Dual-Address Mode (I/O Device to Memory) TMP1942CY/CZ-162 TMP1942CY/CZ Example: DMA transfer of serially received data (SCnBUF) to internal RAM Example DMA settings * Channel used: 0 * Source address: SC1BUF * Destination: 0xFFFF_9800 (physical address) * Number of bytes transferred: 256 Example serial channel settings * Data length: 8 bits, UART * Serial channel: Channel 1 * Transfer rate: 9600 bps DMA (channel 0) is used for transfer. DMA0 is activated by an interrupt received on SIO1. DMA0 settings DCR IMCFL INTCLR DTCR0 SAR0 DAR0 BCR0 CCR0 0xFFFF_F208 0xFFFF_9800 0x0000_00FF 0x80C0_5B0F 27 0 0 0 0 11 1 0 1 1 x 1 1 0 0 0 23 1 7 x 0 0 0 1 0 0 19 0 3 1 1 1 1 0 0 0 0x8000_0000 15 7 0 /* Level = 4 (arbitrary value) */ /* Value of IVR [9:4] */ /* DACM = 000 */ /* SACM = 000 */ /* Physical address of SC1BUF */ /* Physical address of destination */ /* 256 (number of bytes to be transferred) */ xxxx, xxxx, xx10, x100 0x3c 0x0000_0000 /* Reset DMA */ (Contents) 31 1 15 0 SIO channel 1 settings IMCCH INTCLR SC1CR BR1CR 31 15 /* Assign to DMC0 activation source */ /* IVR [9:4], INTRX1 interrupt source */ /* UART mode, 8-bit length, baud rate generator */ /* @fc = 32 MHz (approx. 9615 bps) */ xxxx, xxxx, xx11, 1000 0x32 0x29 0x00 0x1d SC1MOD0 TMP1942CY/CZ-163 TMP1942CY/CZ 3.9 8-Bit Timers (TMRA) The TMP1942 contains twelve 8-bit timer channels (TMRA0-TMRAB). There are six TMRA modules, referred to as TMRA01, TMRA23, TMRA45, TMRA67, TMRA89 and TMRAAB, each of which is comprised of two channels. Each module can operate in the following four modes: * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave output mode (PPG: variable duty with variable cycle) 8-bit pulse width modulation output mode (PWM: variable duty with constant cycle) Figure 3.9.1 shows a block diagram of TMRA01. Each channel consists primarily of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. Each pair of channels also incorporates one prescaler and one timer flip-flop. Timer operation modes and flip-flops are controlled by five registers. The six modules (TMRA01, TMRA23, TMRA45, TMRA67, TMRA89 and TMRAAB) operate independently of each other. Because each module functions the same way except for a few differences as shown in Tables Table 3.9.1 and Table 3.9.2, operation of the TMRA01 only is described here. Table 3.9.1 Specification Differences Among the TMRA Modules Specification External clock input pin Timer flip-flop output pin Timer run register SFR Name (address) Timer registers Timer mode register Timer flip-flop control register Module TMRA01 TA0IN (Shared with PA7) TA1OUT (Shared with PA6) TA01RUN (0xFFFF_F100) TA0REG (0xFFFF_F102) TA1REG (0xFFFF_F103) TA01MOD (0xFFFF_F104) TA1FFCR (0xFFFF_F105) TMRA23 TA2IN (Shared with PB7) TA3OUT (Shared with PB6) TA23RUN (0xFFFF_F108) TA2REG (0xFFFF_F10A) TA3REG (0xFFFF_F10B) TA23MOD (0xFFFF_F10C) TA3FFCR (0xFFFF_F10D) TMRA45 TA4IN (Shared with PC0) TA5OUT (Shared with PC3) TA45RUN (0xFFFF_F110) TA4REG (0xFFFF_F112) TA5REG (0xFFFF_F113) TA45MOD (0xFFFF_F114) TA5FFCR (0xFFFF_F115) External pins Table 3.9.2 Specification Differences Among the TMRA Modules Specification External clock input pin Timer flip-flop output pin Timer run register SFR Name (address) Timer registers Timer mode register Timer flip-flop control register Module TMRA67 TA6IN (Shared with PC1) TA7OUT (Shared with PC5) TA67RUN (0xFFFF_F118) TA6REG (0xFFFF_F11A) TA7REG (0xFFFF_F11B) TA67MOD (0xFFFF_F11C) TA7FFCR (0xFFFF_F11D) TMRA89 TA8IN (Shared with PC2) TA9OUT (Shared with PC7) TA89RUN (0xFFFF_F120) TA8REG (0xFFFF_F122) TA9REG (0xFFFF_F123) TA89MOD (0xFFFF_F124) TA9FFCR (0xFFFF_F125) TMRAAB TAAIN (Shared with PC4) TABOUT (Shared with PD5) TAABRUN (0xFFFF_F128) TAAREG (0xFFFF_F12A) TABREG (0xFFFF_F12B) TAABMOD (0xFFFF_F12C) TABFFCR (0xFFFF_F12D) External pins TMP1942CY/CZ-164 3.9.1 Prescaler run/clear 2 T1 Timer flip-flop TA1FF TA01RUN n Prescaler clock: T0 4 T4 T16 T256 8 16 32 64 128 256 512 TA01RUN Selector TA01RUN Timer flip-flop output: TA1OUT Block diagram of each module External clock input: TA0IN T1 T4 T16 TA01MOD Only a block diagram of TMRA01 is described here. It applies to all other modules with the exception of differences in register, signal and other element names. Figure 3.9.1 TMRA01 Block D iagram 8-bit comparator (CP0) Match 8-bit comparator detection (CP1) TMP1942CY/CZ-165 Register buffer 0 Internal data bus TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG Internal data bus TMP1942CY/CZ TA01RUN TMRA1 interrupt output: INTTA1 TMP1942CY/CZ 3.9.2 Functional description of each circuit (1) Prescaler The TMP1942 has a 9-bit prescaler to supply a clock to TMRA01. The prescaler's input clock T0 has a frequency of fperiph, fperiph/2 or fperiph/4 as selected by SYSCR0 @fc = 32 MHz Peripheral Clock Selection Clock Gear Value 00 (fc) Selected Prescaler Clock 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 3 2 Prescaler Output Clock Resolution T1 fc/2 (0.25 s) fc/2 (0.125 s) fc/2 (0.5 s) 4 T4 fc/2 (1.0 s) 5 4 T16 fc/2 (4.0 s) 7 6 5 8 7 6 T256 fc/2 (64 s) 11 10 9 fc/2 (0.5 s) fc/2 (0.25 s) 3 fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (8.0 s) fc/2 (4.0 s) fc/2 (2.0 s) fc/2 (16 s) 9 fc/2 (32 s) fc/2 (16 s) fc/2 (128 s) 12 fc/2 (2.0 s) 6 5 4 7 6 5 8 7 6 5 4 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.25 s) 3 fc/2 (1.0 s) fc/2 (0.5 s) fc/2 (4.0 s) fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (8.0 s) fc/2 (4.0 s) fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (0.5 s) fc/2 (0.25 s) 3 fc/2 (64 s) 11 10 fc/2 (1.0 s) 5 4 fc/2 (32 s) fc/2 (256 s) 13 12 fc/2 (0.5 s) fc/2 (2.0 s) 6 5 fc/2 (8.0 s) 8 7 fc/2 (128 s) fc/2 (64 s) 11 fc/2 (4.0 s) fc/2 (32 s) 10 9 fc/214 (512 s) fc/2 (256 s) 13 12 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (1.0 s) fc/2 (0.25 s) 3 fc/2 (16 s) fc/2 (8.0 s) 8 7 6 5 7 6 fc/2 (128 s) fc/2 (64 s) 11 10 9 fc/2 (4.0 s) fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (4.0 s) fc/2 (2.0 s) fc/25 (1.0 s) fc/2 (4.0 s) 7 6 5 7 6 5 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.125 s) 2 fc/2 (32 s) fc/2 (16 s) fc/2 (64 s) 11 10 9 fc/2 (0.25 s) 3 fc/2 (1.0 s) 5 4 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) fc/2 (0.5 s) fc/2 (0.25 s) 3 fc/2 (32 s) fc/2 (16 s) fc/2 (64 s) 11 10 9 fc/2 (1.0 s) 5 4 fc/2 (0.5 s) fc/2 (1.0 s) 5 fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (4.0 s) fc/2 (2.0 s) fc/2 (1.0 s) fc/2 (32 s) fc/2 (16 s) fc/2 (64 s) 11 10 9 11 (fc/8) 01 (fperiph/2) 10 (fperiph) fc/2 (32 s) fc/2 (16 s) Note 1: The prescaler's output clock Tn must be selected such that the relationship Tn < fsys/2 is satisfied (i.e., Tn must be slower than fsys/2). Note 2: Do not change the clock gear value while the timer is operating. Note 3: The - character meams "Don't use". TMP1942CY/CZ-166 TMP1942CY/CZ (2) Up-counters (UC0 and UC1) UC0 and UC1 are 8-bit binary counters which count up synchronously with the input clock selected in timer mode register TA01MOD. The input clock for UC0 is either the external clock entered via the TA0IN pin or one of the three prescaler output clocks, T1, T4 or T16, according to the value set in TA01MOD TMP1942CY/CZ-167 TMP1942CY/CZ Up-counter Comparator (CP0) Timer register 0 (TA0REG) Y Shift trigger Register buffer 0 Write Selector B PPG cycle match detection n PWM 2 -1 overflow Write to TA0REG A S TA01RUN Figure 3.9.2 Structure of Timer Register 0 (TA0REG) Note: When data is written to TA0REG, the same address is allocated to the timer register and the register buffer. When Each register is a write-only register and cannot be read. (4) Comparator (CP0) This circuit compares the up-counter value with the timer register value. When the values match, it clears the up-counter to 0 and at the same time generates an INTTA0 or INTTA1 interrupt. Also, if timer flip-flop inversion is enabled, it inverts the timer flip-flop value. (5) Timer flip-flop (TA1FF) The timer flip-flop TA1FF is designed to be inverted by a match detection signal from the comparator. Inversion can be disabled or enabled by setting TA1FFCR TMP1942CY/CZ-168 TMP1942CY/CZ 3.9.3 Register description TMRA01 run register 7 Bit symbol TA01RUN (0xFFFF_F100) Read/Write After reset TA0RDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TA0REG double-buffer. 0 1 Disable Enable I2TA01: TA1RUN: TA0RUN: Operation in IDLE mode Operation of timer 1 Operation of timer 0 6 -- -- -- 5 -- -- -- 4 -- -- -- 0 IDLE 0: Idle 0 3 I2TA01 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 Timer Run/Stop Control 0: Stop and cleared 1: Operate 1: Count TA01PRUN: Operation of the prescaler Note: TA01RUN bits 4, 5 and 6 are undefined when read. TMRA23 run register 7 Bit symbol TA23RUN (0xFFFF_F108) Read/Write After reset TA2RDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TA2REG double-buffer. 0 1 Disable Enable I2TA23: TA3RUN: TA2RUN: Operation in IDLE mode Operation of timer 3 Operation of timer 2 6 -- -- -- 5 -- -- -- 4 -- -- -- 0 IDLE 0: Idle 0 3 I2TA23 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 Timer Run/Stop Control 0: Stop and cleared 1: Operate 1: Count TA23PRUN: Operation of the prescaler Note: TA23RUN bits 4, 5 and 6 are undefined when read. Figure 3.9.3 TMRA Registers TMP1942CY/CZ-169 TMP1942CY/CZ TMRA45 run register 7 TA45RUN (0xFFFF_F110 ) Bit symbol Read/Write After reset TA4RDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TA4REG double-buffer. 0 1 Disable Enable I2TA45: TA5RUN: TA4RUN: Operation in IDLE mode Operation of timer 5 Operation of timer 4 6 -- -- -- 5 -- -- -- 4 -- -- -- IDLE 0: Idle 0 0 3 I2TA45 2 R/W 0 0 Timer Run/Stop Control 0: Stop and cleared 1 0 TA4RUN TA45PRUN TA5RUN 1: Operate 1: Count TA45PRUN: Operation of the prescaler Note: TA45RUN bits 4, 5 and 6 are undefined when read. TMRA67 run register 7 TA67RUN (0xFFFF_F118) Bit symbol Read/Write After reset TA6RDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TA6REG double-buffer. 0 1 Disable Enable I2TA67: TA7RUN: TA6RUN: Operation in IDLE mode Operation of timer 7 Operation of timer 6 6 -- -- -- 5 -- -- -- 4 -- -- -- IDLE 0: Idle 0 0 3 I2TA67 2 R/W 0 0 Timer Run/Stop Control 0: Stop and cleared 1 0 TA6RUN TA67PRUN TA7RUN 1: Operate 1: Count TA67PRUN: Operation of the prescaler Note: TA67RUN bits 4, 5 and 6 are undefined when read. Figure 3.9.4 TMRA Registers TMP1942CY/CZ-170 TMP1942CY/CZ TMRA89 run register 7 TA89RUN (0xFFFF_F120 ) Bit symbol Read/Write After reset TA8RDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TA8REG double-buffer. 0 1 Disable Enable I2TA89: TA9RUN: TA8RUN: Operation in IDLE mode Operation of timer 9 Operation of timer 8 6 -- -- -- 5 -- -- -- 4 -- -- -- 0 IDLE 0: Idle 0 3 I2TA89 2 R/W 0 0 Timer Run/Stop Control 0: Stop and cleared 1 0 TA8RUN TA89PRUN TA9RUN 1: Operate 1: Count TA89PRUN: Operation of the prescaler Note: TA89RUN bits 4, 5 and 6 are undefined when read. TMRAAB run register 7 TAABRUN (0xFFFF_F128) Bit symbol Read/Write After reset TAARDE R/W 0 Double Function Buffer 0: Disable 1: Enable This bit controls the TAAREG double-buffer. 0 1 Disable Enable I2TAAB: TABRUN: TAARUN: Operation in IDLE mode Operation of timer B Operation of timer A 6 -- -- -- 5 -- -- -- 4 -- -- -- 0 IDLE 0: Idle 0 3 I2TAAB 2 R/W 0 0 Timer Run/Stop Control 0: Stop and cleared 1 0 TAARUN TAABPRUN TABRUN 1: Operate 1: Count TAABPRUN: Operation of the prescaler Note: TAABRUN bits 4, 5 and 6 are undefined when read. Figure 3.9.5 TMRA Registers TMP1942CY/CZ-171 TMP1942CY/CZ TMRA01 mode register 7 Bit symbol TA01MOD (0xFFFF_F104) Read/Write After reset TA01M1 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 -1 8 7 6 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 TMRA1 source clock TMRA0 source clock 00: TA0IN pin input 01: T1 10: T4 11: T16 TMRA0 input clock 00 01 10 11 External input (TA0IN pin input) T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRA1 input clock TA01MOD 00 01 10 11 TMRA0 match detection T1 T16 T256 TMRA0 overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRA01 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRA0), 8-bit timer (TMRA1) Figure 3.9.6 TMRA Registers TMP1942CY/CZ-172 TMP1942CY/CZ TMRA23 mode register 7 TA23MOD (0xFFFF_F10C) Bit symbol Read/Write After reset 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 8 7 6 6 TA01M0 5 PWM01 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA2TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 TA01M1 TMRA3 source clock TMRA2 source clock 00: TA2IN pin input 01: T1 10: T4 11: T16 TMRA2 input clock 00 01 10 11 External input (TA2IN pin input) T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRA3 input clock TA23MOD 00 01 10 11 TMRA2 match detection T1 T16 T256 TMRA2 overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRA23 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRA2), 8-bit timer (TMRA3) Figure 3.9.7 TMRA Registers TMP1942CY/CZ-173 TMP1942CY/CZ TMRA45 mode register 7 Bit symbol TA45MOD (0xFFFF_F114) Read/Write After reset TA45M1 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 6 TA45M0 0 5 PWM41 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 -1 8 7 6 4 PWM40 0 R/W 3 TA5CLK1 0 00: TA4TRG 01: T1 10: T16 11: T256 2 TA5CLK0 0 1 TA4CLK1 0 00: TA4IN 01: T1 10: T4 11: T16 0 TA4CLK0 0 TMRA5 source clock TMRA4 source clock TMRA4 input clock 00 TA4IN 01 10 11 T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRA5 input clock TA45MOD 00 01 10 11 TMRA4 match detection T1 T16 T256 TMRA4 overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRA45 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRA4), 8-bit timer (TMRA5) Figure 3.9.8 TMRA Registers TMP1942CY/CZ-174 TMP1942CY/CZ TMRA67 mode register 7 Bit symbol TA67MOD (0xFFFF_F11C) Read/Write After reset TA67M1 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 6 TA67M0 0 5 PWM61 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 -1 8 7 6 4 PWM60 0 R/W 3 TA7CLK1 0 00: TA6TRG 01: T1 10: T16 11: T256 2 TA7CLK0 0 1 TA6CLK1 0 00: TA6IN 01: T1 10: T4 11: T16 0 TA6CLK0 0 TMRA7 source clock TMRA6 source clock TMRA6 input clock 00 01 10 11 TA6IN T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRA7 input clock TA67MOD 00 01 10 11 TMRA6 match detection T1 T16 T256 TMRA6 overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRA67 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRA6), 8-bit timer (TMRA7) Figure 3.9.9 TMRA Registers TMP1942CY/CZ-175 TMP1942CY/CZ TMRA89 mode register 7 TA89MOD (0xFFFF_F124) Bit symbol Read/Write After reset 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 -1 8 7 6 6 TA89M0 5 PWM81 4 PWM80 0 R/W 3 TA9CLK1 0 00: TA8TRG 01: T1 10: T16 11: T256 2 TA9CLK0 0 1 TA8CLK1 0 00: TA8IN 01: T1 10: T4 11: T16 0 TA8CLK0 0 TA89M1 TMRA9 source clock TMRA8 source clock TMRA8 input clock 00 01 10 11 TA8IN T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRA9 input clock TA89MOD 00 01 10 11 TMRA8 match detection T1 T16 T256 TMRA8 overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRA89 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRA8), 8-bit timer (TMRA9) Figure 3.9.10 TMRA Registers TMP1942CY/CZ-176 TMP1942CY/CZ TMRAAB mode register 7 Bit symbol TAABMOD (0xFFFF_F12C) Read/Write After reset TAABM1 0 Operating mode 00: 8-bit timer Function 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 6 TAABM0 0 5 PWMA1 0 PWM cycle 00: Reserved 01: 2 -1 10: 2 -1 11: 2 -1 8 7 6 4 PWMA0 0 R/W 3 TABCLK1 0 00: TAATRG 01: T1 10: T16 11: T256 2 TABCLK0 0 1 TAACLK1 0 00: TAAIN 01: T1 10: T4 11: T16 0 TAACLK0 0 TMRAB source clock TMRAA source clock TMRAA input clock 00 01 10 11 TAAIN T1 T4 T16 (prescaler) (prescaler) (prescaler) TMRAB input clock TAABMOD 00 01 10 11 TMRAA match detection T1 T16 T256 TMRAA overflow output 16-bit timer mode Selects cycle in 8-bit PWM mode 00 01 10 11 Reserved (2 -1) x clock source 6 7 8 (2 -1) x clock source (2 -1) x clock source Selects operating mode for TMRAAB 00 01 10 11 8-bit timer x 2 16-bit timer 8-bit programmable square wave output 8-bit PWM (TMRAA), 8-bit timer (TMRAB) Figure 3.9.11 TMRA Registers TMP1942CY/CZ-177 TMP1942CY/CZ TMRA1 flip-flop control register 7 TA1FFCR (0xFFFF_F105) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFF1C1 2 TAFF1C0 R/W 0 0 Selects TA1FF inversion signal. 0: TMRA0 1: TMRA1 00: Invert TA1FF value Controls TA1FF (soft inversion). inversion. 01: Set TA1FF to 1. 0: Disable 10: Clear TA1FF to 0. inversion. 11: Don't care 1: Enable (These bits are inversion. always 11 when read.) 1 TAFF1IE 0 TAFF1IS Function Selects the signal which inverts timer flip-flop 1 (TA1FF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRA0 Inverted by TMRA1 Note: TA1FFCR bits 4, 5, 6 and 7 are undefined when read. TMRA3 flip-flop control register 7 TA3FFCR (0xFFFF_F10D) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFF3C1 2 TAFF3C0 R/W 0 Controls TA3FF inversion. 0 Selects TA3FF inversion signal. 00: Invert TA3FF value (soft inversion). 01: Set TA3FF to 1. Function 10: Clear TA3FF to 0. 11: Don't care (These bits are always 11 when read.) 1 TAFF3IE 0 TAFF3IS 0: Disable inversion. 0: TMRA2 1: Enable 1: TMRA3 inversion. Selects the signal which inverts timer flip-flop 3 (TA3FF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRA2 Inverted by TMRA3 Note: TA3FFCR bits 4, 5, 6 and 7 are undefined when read. Figure 3.9.12 TMRA Registers TMP1942CY/CZ-178 TMP1942CY/CZ TMRA5 flip-flop control register 7 TA5FFCR (0xFFFF_F115) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFF5C1 2 TAFF5C0 R/W 0 Controls TA5FF inversion. 0 Selects TA5FF inversion signal. 00: Invert TA5FF value (soft inversion). 01: Set TA5FF to 1. Function 10: Clear TA5FF to 0. 11: Don't care (These bits are always 11 when read.) 1 TAFF5IE 0 TAFF5IS 0: Disable inversion. 0: TMRA4 1: Enable 1: TMRA5 inversion. Selects the signal which inverts timer flip-flop 5 (TA5FF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRA4 Inverted by TMRA5 Note: TA5FFCR bits 4, 5, 6 and 7 are undefined when read. TMRA7 flip-flop control register 7 TA7FFCR (0xFFFF_F11D) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFF7C1 2 TAFF7C0 R/W 0 Controls TA7FF inversion. 0 Selects TA7FF inversion signal. 00: Invert TA7FF value (soft inversion). 01: Set TA7FF to 1. Function 10: Clear TA7FF to 0. 11: Don't care (These bits are always 11 when read.) 1 TAFF7IE 0 TAFF7IS 0: Disable inversion. 0: TMRA6 1: Enable 1: TMRA7 inversion. Selects the signal which inverts timer flip-flop 7 (TA7FF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRA6 Inverted by TMRA7 Note: TA7FFCR bits 4, 5, 6 and 7 are undefined when read. Figure 3.9.13 TMRA Registers TMP1942CY/CZ-179 TMP1942CY/CZ TMRA9 flip-flop control register 7 TA9FFCR (0xFFFF_F125) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFF9C1 2 TAFF9C0 R/W 0 Controls TA9FF inversion. 0 Selects TA9FF inversion signal. 00: Invert TA9FF value (soft inversion). 01: Set TA9FF to 1. Function 10: Clear TA9FF to 0. 11: Don't care (These bits are always 11 when read.) 1 TAFF9IE 0 TAFF9IS 0: Disable inversion. 0: TMRA8 1: Enable 1: TMRA9 inversion. Selects the signal which inverts timer flip-flop 9 (TA9FF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRA8 Inverted by TMRA9 Note: TA9FFCR bits 4, 5, 6 and 7 are undefined when read. TMRAB flip-flop control register 7 TABFFCR (0xFFFF_F12D) Bit symbol Read/Write After reset -- -- -- 6 -- -- -- 5 -- -- -- 4 -- -- -- 1 1 3 TAFFBC1 2 TAFFBC0 R/W 0 Controls TABFF inversion. 0 Selects TABFF inversion signal. 00: Invert TABFF value (soft inversion). 01: Set TABFF to 1. Function 10: Clear TABFF to 0. 11: Don't care (These bits are always 11 when read.) 1 TAFFBIE 0 TAFFBIS 0: Disable inversion. 0: TMRAA 1: Enable 1: TMRAB inversion. Selects the signal which inverts timer flip-flop B (TABFF). (Don't care unless in 8-bit timer mode) 0 1 Inverted by TMRAA Inverted by TMRAB Note: TABFFCR bits 4, 5, 6 and 7 are undefined when read. Figure 3.9.14 TMRA Registers TMP1942CY/CZ-180 TMP1942CY/CZ 3.9.4 Functional description for each mode (1) 8-bit timer mode TMRA0 and TMRA1 can be used as 8-bit interval timers independently of each other. You must stop TMRA0 and TMRA1 before attempting to set their functions or count data. a. Generating interrupts periodically The following description uses TMRA1 as an example. To generate a TRAM1 interrupt, INTTA1, at certain intervals, first stop timer 1 and set the operating mode, input clock and cycle in the TA01MOD and TA1REG registers. Next, enable the INTTA1 interrupt and start timer 1. Example: To generate INTTA1 interrupts every 20 s with fc = 32 MHz, set the registers in the following sequence: *Clock conditions System clock: Prescaler clock: MSB 7 TA01RUN TA01MOD TA1REG IMC5LH TA01RUN - 0 0 X - 6 - 0 1 X X 5 X X 0 1 X 4 X X 1 1 X 3 - 1 0 0 - LSB 2 - 0 0 1 1 1 0 X 0 0 1 0 - X 0 1 - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and set input clock to T1 (0.25 s resolution, fc = 32 MHz). Write 20 s/T1 = 80 (50H) to TA1REG. Enable INTTA1 and set interrupt level = 5 and rising edge detection. Start TMRA1. High-speed (fc) fperiph/4 (fperiph = fsys) Note: X = Don't care; "--" = No change For a description of input clock selection, refer to Table 3.9.3. Note: The input clocks for TMRA0 and TMRA1 differ as shown below. TMRA0: TA0IN pin input, T1, T4 or T16 TMRA1: TMRA0 match detection signal, T1, T16 or T256 TMP1942CY/CZ-181 TMP1942CY/CZ b. Outputting a 50% duty cycle square wave Invert the value of timer flip-flop TA1FF at certain intervals and forward the inverted value to the timer flip-flop output pin, TA1OUT. Example: To output a 1.5-s cycle square wave with fc = 32 MHz on the TA1OUT pin, set each register in the following sequence. In this example TMRA1 is used to show how to set the registers, although either TMRA0 or TMRA1 may be used. *Clock conditions System clock: High-speed clock gear: Prescaler clock: 7 TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN - 0 0 X - - - 6 X 0 0 X - - X 5 X X 0 X - - X 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 - - 1 1 0 - 1 1 1 1 1 0 - - 1 1 - - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and set input clock to T1 (0.25 s resolution, fc = 32 MHz). Write (1.5 s/T1)/2 = 3 to TA1REG. Clear TA1FF to 0 and set it to be cleared by match detection signal from TMRA1. Set PA6 to TA1OUT output pin. Start TMRA1. High-speed (fc) x 1 (fc) fperiph/4 (fperiph = fsys) Note: X = Don't care; "--" = No change T1 TA01RUN Figure 3.9.15 Square Wave Output Timing (50% Duty Cycle) c. Using a match signal from TMRA0 to make TMRA1 count Select 8-bit timer mode and set the TMRA1 input clock to the TMRA0 comparator output. Comparator TMRA0 match output TMRA0 up-counter (when TA0REG =5) TMRA1 up-counter (when TA1REG =2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.9.16 TMRA1 Counting Based on TMRA0 TMP1942CY/CZ-182 TMP1942CY/CZ (2) 16-bit timer mode TMRA0 and TMRA1 can be used together as a 16-bit interval timer. To select 16-bit timer mode, set TA01MOD *Clock conditions System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x 1 (fc) fperiph/4 (fperiph = fsys) With T16 (= 4.0 s at 32 MHz) used as the input clock, 0.2 s/4.0 s = 50000 = C350H Therefore, TA1REG must be set to 03H and TA0REG to 50H. A TMRA0 comparator output is generated each time the up-counter UC0 and timer register TA0REG match (the up-counter UC0 is not cleared). In this case INTTA0 is not generated. The TMRA1 comparator outputs a match detection signal at each comparator timing when the up-counter UC1 and timer register TA1REG match. If the comparators in both TMRA0 and TMRA1 output a match detection signal at the same time, the up-counters UC0 and UC1 will be cleared to 0 and an INTTA1 interrupt is generated. Also, if inversion is enabled, the value of timer flip-flop TA1FF will be inverted. Example: TA1REG = 04H and TA0REG = 80H Up-counter values 0000H (UC1 and UC0) Match detection signal from TMRA0 comparator Interrupt INTTA1 Timer output TA1OUT Invert 0080H 0180H 0280H 0380H 0480H Figure 3.9.17 Timer Output in 16-Bit Timer Mode TMP1942CY/CZ-183 TMP1942CY/CZ (3) 8-bit PPG (programmable square wave) output mode A square wave of any frequency with any duty cycle can be output using TMRA0. Either Low-active or High-active output pulses can be selected. TMRA1 cannot be used in this mode. The square wave is forwarded to TA1OUT (shared with PA6). tH tL t TA0REG and up-counter 0 match (generating INTTA0) TA1REG and up-counter 0 match (generating INTTA1) TA1OUT TA0REG TA1REG Figure 3.9.18 8-Bit PPG Output Waveform This mode is used to output a programmable square wave by inverting the timer output every time the 8-bit up-counter UC0 matches the timer registers TA0REG and TA1REG. However, the condition (TA0REG set value) < (TA1REG set value) must be satisfied. Although the up-counter UC1 of TMRA1 cannot be used in this mode, TA01RUN TA1OUT Selector T1 T4 T16 TA01RUN TA1FF TA1FFCR TA01MOD INTTA0 INTTA1 Selector TA0REG-WR TA0REG Shift trigger Register buffer TA1REG TA01RUN Internal data bus Figure 3.9.19 8-Bit PPG Output Mode Block Diagram TMP1942CY/CZ-184 TMP1942CY/CZ If TA0REG has its double-buffer enabled in this mode, the value in the register buffer is shifted into TA0REG when TA1REG and UC0 match. If it is necessary to change the duty cycle, using the double-buffer facilitates satisfying the requirements for small duty cycle waveforms. TA0REG and upcounter 0 match TA1REG and upcounter 0 match TA0REG (compare value) Register buffer (Up-counter = Q1) (Up-counter = Q2) Shift to register buffer Q2 Q1 Q2 Q3 Write to TA0REG (register buffer) Figure 3.9.20 Register Buffer Operation Example: To output a 1/4 duty cycle 50-kHz pulse (fc = 32 MHz) 20 s *Clock conditions System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x 1 (fc) fperiph/4 (fperiph = fsys) Calculate the values to be set in the timer registers as follows: To obtain a frequency of 50 kHz, generate a waveform with a period t = 1/50 kHz = 20 s. When T1 = 0.25 s (at fc = 32 MHz), 20 s/0.25 s = 80 Therefore, TA1REG must be set to 80 (= 50H). Next, to obtain a 1/4 duty cycle, using the formula t x 1/4 = 20 s x 1/4 = 5 s, 5 s/0.25 s = 20 Therefore, TA0REG must be set to 20 (= 14H). 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 0 1 0 0 X 6 X 0 0 1 X 5 X X 0 0 X 4 X X 1 1 X 3 - X 0 0 0 2 0 X 1 0 1 1 0 0 0 0 1 0 0 1 0 0 X Stop TMRA0 and TMRA1 and clear them to 0. Select 8-bit PPG mode and set input clock to T1. Write 14H. Write 50H. Set TA1FF and enable inversion. If these bits are set to 10, Low-active output waveform will be obtained. P7CR P7FC TA01RUN - - 1 - - X - - X - - X - - - - - 1 1 1 1 - - 1 Set PA6 to TA1OUT output pin. Start TMRA0 and TMRA1. Note: X = Don't care; "--" = No change TMP1942CY/CZ-185 TMP1942CY/CZ (4) 8-bit PWM output mode This mode, only available for TMRA0, can output PWM pulses with up to 8-bit resolution. PWM output is forwarded to the TA1OUT pin (shared with PA6). In this mode TMRA1 can be used as an 8-bit timer. Timer output is inverted when the up-counter UC0 and the value set in the timer register TA0REG match. It is also inverted when a 2n-1 counter overflow occurs (n = 6, 7 or 8 as specified in TA01MOD TA0REG and up-counter 0 match 2 -1 overflow (INTTA0 interrupt) TA1OUT n tPWM (PWM cycle) Figure 3.9.21 8-Bit PWM Output Waveform Figure 3.9.22 shows a block diagram of 8-bit PWM output mode. TA01RUN (UC 0) TA1OUT TA1FFCR Clear TA1FF Invert TA01MOD 2 -1 overflow control n TA01MOD Overflow Comparator INTTA0 TA0REG Selector Shift trigger Register buffer TA0REG-WR TA01RUN Figure 3.9.22 8-Bit PWM Output Mode Block Diagram TMP1942CY/CZ-186 TMP1942CY/CZ If TA0REG has its double-buffer enabled in this mode, the value in the register buffer is shifted into TA0REG upon the detection of a 2n-1 overflow. Using the double-buffer facilitates satisfying the requirements for small duty cycle waveforms. TA0REG and up-counter 0 match 2 -1 overflow TA0REG (compare value) Register buffer Q1 Q2 Shift to TA0REG Q2 Q3 Write to TA0REG (register buffer) n Up-counter = Q1 Up-counter = Q2 Figure 3.9.23 Register Buffer Operation Example: To output the following PWM waveform on the TA1OUT pin using TMRA0 when fc = 32 MHz 18 s 31.75 s *Clock conditions System clock: High-speed clock gear: Prescaler clock: High-speed (fc) x 1 (fc) fperiph/4 (fperiph = fsys) To achieve a PWM cycle of 31.75 s with T1 = 0.25 s (at fc = 32 MHz), the following equation must be satisfied: 31.75 s/0.25 s = 127 = 2n-1 Therefore, n must be set to 7. Since the Low-level period is 18 s and T1 = 0.25 s, 18 s/0.25 s = 72 = 48H Therefore, TA0REG must be set to 48H. MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN - 1 0 X - - 1 6 X 1 1 X - - X 5 X 1 0 X - - X 4 X 0 0 X - - X LSB 3 - - 1 1 - - - 2 - - 0 0 - - 1 1 - 0 0 1 1 1 - 0 0 1 0 X - - 1 Stops TMRA0 and clear it to 0. Select 8-bit PWM mode (cycle = 2 -1) and set input clock to T1. Write 48H. Clear TA1FF and enable inversion. 7 Set PA6 to TA1OUT output pin. Start TMRA0. Note: X = Don't care; "--" = No change TMP1942CY/CZ-187 TMP1942CY/CZ Table 3.9.4 PWM Periods @fc = 32 MHz Peripheral Clock Selection Clock Gear Value Selected Prescaler Clock 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) PWM Period 2 -1 6 27 - 1 T16 252 s 126 s 63 s 504 s 252 s 126 s 504 s 252 s 28 - 1 T16 508 s 254 s 127 s 508 s 254 s T1 15.8 s 7.9 s 31.5 s 15.8 s 63 s 31.5 s 126 s 63 s 15.8 s 7.9 s 15.8 s T4 63 s 31.5 s 15.8 s 126 s 63 s 31.5 s 126 s 63 s T1 31.8 s 63.5 s 31.8 s 63.5 s T4 127 s 31.8 s 127 s 63.5 s T1 63.8 s 63.8 s T4 T16 255 s 1020 s 63.8 s 255 s 00 (fc) 15.9 s 63.5 s 31.9 s 127.5 s 510 s 254 s 1016 s 127.5 s 510 s 2040 s 255 s 1020 s 127.5 s 510 s 01 (fc/2) 0 (fgear) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 252 s 1008 s 127 s 508 s 2032 s 255 s 1020 s 4080 s 254 s 1016 s 127.5 s 510 s 2040 s 127 s 508 s 255 s 1020 s 504 s 2016 s 254 s 1016 s 4064 s 510 s 2040 s 8160 s 252 s 1008 s 127 s 126 s 63 s 31.5 s 15.8 s 63 s 31.5 s 15.8 s 63 s 31.5 s 63 s 504 s 252 s 126 s 63 s 252 s 126 s 63 s 252 s 126 s 63 s 252 s 126 s 63 s 31.8 s 31.8 s 508 s 2032 s 255 s 1020 s 4080 s 254 s 1016 s 127 s 31.8 s 127 s 63.5 s 31.8 s 127 s 63.5 s 127 s 508 s 254 s 127 s 508 s 254 s 127 s 508 s 254 s 127 s 508 s 254 s 127 s 63.8 s 63.8 s 510 s 2040 s 255 s 1020 s 63.8 s 255 s 11 (fc/8) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 00 (fc) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 15.9 s 63.5 s 31.9 s 127.5 s 510 s 255 s 1020 s 127.5 s 510 s 63.8 s 255 s 255 s 1020 s 127.5 s 510 s 255 s 510 s 255 s 255 s 1020 s 01 (fc/2) 1 (fc) 10 (fc/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 00 (fperiph/4) 11 (fc/8) 01 (fperiph/2) 10 (fperiph) Note 1: The prescaler's output clock Tn must be selected such that the relationship Tn < fsys/2 is satisfied (i.e., Tn must be slower than fsys/2). Note 2: Do not change the clock gear value while the timer is running. Note 3: The -- character means "Don't use". TMP1942CY/CZ-188 TMP1942CY/CZ (5) Summary of operating mode settings Table 3.9.5 summarizes the settings for TMRA01 for each mode. Table 3.9.5 Register Settings for Each Timer Mode Register Name Register Field Name Function TA01MOD Low-order timer match, T1, T16, T256 (00, 01, 10, 11) TA1FFCR TAFF1IS Timer F/F Low-order timer inverting signal input clock selection External, T1, T4, T16 (00, 01, 10, 11) External, 0: Low-order timer output 1: High-order timer output 8-bit timer x 2 channels 00 16-bit timer mode 01 T1, T4, T16 (00, 01, 10, 11) External, T1, T4, T16 (00, 01, 10, 11) External, T1, T4, T16 (00, 01, 10, 11) 8-bit PPG x 1 channel 8-bit PWM x 1 channel 8-bit timer x 1 channel (Note) "--" = Don't care 10 6 2 - 1, 2 - 1, 8 2 -1 (01, 10, 11) 7 T1, 16, T256 (01, 10, 11) 11 PWM output Note: In 8-bit PWM generation mode, the UC1 can be used as an 8-bit timer. However, the match-detect output from the UC0 can not be used as a clock source for the UC1, and the timer output is not available for the UC1. TMP1942CY/CZ-189 TX1942CY/CZ 3. 3.10 16-Bit Timers/Event Counters (TMRBn) The TMP1942 contains fourteen multi-function 16-bit timer/event counter channels (TMRB0-TMRBD). TMRBn can operate in the following four modes: * * * * 16-bit interval timer mode 16-bit event counter mode 16-bit programmable square wave output (PPG) mode 2-phase pulse input counter mode (only for TMRB2 and TMRB3) In addition, when used in combination with the capture function, TMRBn can be run in the following modes: * * * Frequency measurement mode Pulse width measurement mode Time difference measurement mode Each channel consists primarily of a 16-bit up-counter, two 16-bit timer registers (one with a double-buffer structure), two 16-bit capture registers, two comparators, capture input controller, and a timer flip-flop with accompanying control circuit. Timer operating modes and flip-flops are controlled by eleven registers. All channels TMRB0 to TMRBD operate independently of each other. Because each channel functions the same way except for the 2-phase pulse counter function and a few other differences as shown in Tables 3.10.1 to 3.10.2, operation of the TMRB0 only is described here, with an explanation of the 2-phase pulse counter function for TMRB2 and TMRB3. Table 3.10.1 Specification Differences Among the TMRB Channels Specification External clock/ capture trigger input pins Capture trigger timer Timer flip-flop output pin Timer run register Timer mode register Timer flip-flop control register Channel TMRB0 TB0IN0 (Shared with PA0) TB0IN1 (Shared with PA1) TA3OUT TMRB1 TB1IN0 (Shared with PA3) TB1IN1 (Shared with PA4) TA3OUT TMRB2 TB2IN0 (Shared with PB0) TB2IN1 (Shared with PB1) TA3OUT TMRB3 TB3IN0 (Shared with PB3) TB3IN1 (Shared with PB4) TA3OUT External pins TB0OUT (Shared with PA2) TB1OUT (Shared with PA5) TB2OUT (Shared with PB2) TB3OUT (Shared with PB5) TB0RUN (0xFFFF_F140) TB0MOD (0xFFFF_F142) TB0FFCR (0xFFFF_F143) TB0RG0L (0xFFFF_F148) TB1RUN (0xFFFF_F150) TB1MOD (0xFFFF_F152) TB1FFCR (0xFFFF_F153) TB1RG0L (0xFFFF_F158) TB1RG0H (0xFFFF_F159) TB1RG1L (0xFFFF_F15A) TB2RUN (0xFFFF_F160) TB2MOD (0xFFFF_F162) TB2FFCR(0xFFFF_F163) TB2RG0L (0xFFFF_F168) TB2RG1L (0xFFFF_F16A) TB3RUN (0xFFFF_F170) TB3MOD (0xFFFF_F172) TB3FFCR (0xFFFF_F173) TB3RG0L (0xFFFF_F178) TB3RG1L (0xFFFF_F17A) Register name Timer registers (address) TB0RG0H (0xFFFF_F149) TB0RG1L (0xFFFF_F14A) TB0RG1H (0xFFFF_F14B) TB0CP0L (0xFFFF_F14C) TB2RG0H (0xFFFF_F169) TB3RG0H (0xFFFF_F179) TB1RG1H (0xFFFF_F15B) TB2RG1H (0xFFFF_F16B) TB3RG1H (0xFFFF_F17B) TB1CP0L (0xFFFF_F15C) TB1CP1L (0xFFFF_F15E) TB1CP1H (0xFFFF_F15F) TB2CP0L (0xFFFF_F16C) TB2CP1L (0xFFFF_F16E) TB2CP1H (0xFFFF_F16F) TB3CP0L (0xFFFF_F17C) TB3CPIL (0xFFFF_F17E) TB3CPIH (0xFFFF_F17F) Capture registers TB0CP0H (0xFFFF_F14D) TB0CP1L (0xFFFF_F14E) TB0CP1H (0xFFFF_F14F) TB1CP0H (0xFFFF_F15D) TB2CP0H (0xFFFF_F16D) TB3CP0H (0xFFFF_F17D) TMP1942CY/CZ-190 TX1942CY/CZ Table 3.10.2 Specification Differences Among the TMRB Channels Specification External clock/ capture trigger input pins Capture trigger timer Timer flip-flop output pin Timer run register Timer mode register Timer flip-flop control register Channel TMRB4 TB4IN0 (Shared with PB2) TB4IN1 (Shared with PB5) TA3OUT TA3OUT -- TA3OUT -- TMRB5 TMRB6 TMRB7 TB4IN0 (Shared with P95) TB4IN1 (Shared with P96) TA3OUT External pins TB4OUT (Shared with P92) TB5OUT (Shared with P93) TB6OUT (Shared with P94) TB7OUT (Shared with P97) TB4RUN (0xFFFF_F180) TB4MOD (0xFFFF_F182) TB4FFCR (0xFFFF_F183) TB4RG0L (0xFFFF_F188) TB5RUN (0xFFFF_F190) TB5MOD (0xFFFF_F192) TB5FFCR (0xFFFF_F193) TB5RG0L (0xFFFF_F198) TB5RG0H (0xFFFF_F199) TB5RG1L (0xFFFF_F19A) TB6RUN (0xFFFF_F1A0) TB6MOD (0xFFFF_F1A2) TB6FFCR(0xFFFF_F1A3) TB6RG0L (0xFFFF_F1A8) TB7RUN (0xFFFF_F1B0) TB7MOD (0xFFFF_F1B2) TB7FFCR (0xFFFF_F1B3) TB7RG0L (0xFFFF_F1B8) Register name Timer registers (address) TB4RG0H (0xFFFF_F189) TB4RG1L (0xFFFF_F18A) TB4RG1H (0xFFFF_F18B) TB4CP0L (0xFFFF_F18C) TB6RG0H (0xFFFF_F1A9) TB7RG0H (0xFFFF_F1B9) TB6RG1L (0xFFFF_F1AA) TB7RG1L (0xFFFF_F1BA) TB5RG1H (0xFFFF_F19B) TB6RG1H (0xFFFF_F1AB) TB7RG1H (0xFFFF_F1BB) TB5CP0L (0xFFFF_F19C) TB5CP1L (0xFFFF_F19E) TB5CP1H (0xFFFF_F19F) TB6CP0L(0xFFFF_F1AC) TB6CP1L (0xFFFF_F1AE) TB7CP0L (0xFFFF_F1BC) TB7CP0H(0xFFFF_F1BD) TB7CPIL (0xFFFF_F1BE) Capture registers TB4CP0H (0xFFFF_F18D) TB4CP1L (0xFFFF_F18E) TB4CP1H (0xFFFF_F18F) TB5CP0H (0xFFFF_F19D) TB6CP0H(0xFFFF_F1AD) TB6CP1H (0xFFFF_F1AF) TB7CPIH (0xFFFF_F1BF) Table 3.10.3 Specification Differences Among the TMRB Channels Specification External clock/ Channel TMRB8 TB8IN0 (Shared with PC6) TB8IN1 (Shared with PC7) TA5OUT -- TB8RUN (0xFFFF_F1C0) TB8MOD (0xFFFF_F1C2) -- TB8RG0L (0xFFFF_F1C8) TMRB9 TB9IN0 (Shared with PD0) TB8IN1 (Shared with PD1) TA5OUT -- TB9RUN (0xFFFF_F1D0) TB9MOD (0xFFFF_F1D2) -- TB9RG0L (0xFFFF_F1D8) TMRBA TBAIN0 (Shared with PD5) TBAIN1 (Shared with PD6) TA5OUT -- TBARUN (0xFFFF_F1E0) TBAMOD (0xFFFF_F1E2) -- TMRBB -- TA5OUT -- TBBRUN (0xFFFF_F1F0) TBBMOD (0xFFFF_F1F2) -- External pins capture trigger input pins Capture trigger timer Timer flip-flop output pin Timer run register Timer mode register Timer flip-flop control register TBARG0L (0xFFFF_F1E8) TBBRG0L (0xFFFF_F1F8) Register name Timer registers (address) TB8RG0H (0xFFFF_F1C9) TB9RG0H (0xFFFF_F1D9) TBARG0H (0xFFFF_F1E9) TBBRG0H (0xFFFF_F1F9) TB8RG1L (0xFFFF_F1CA) TB9RG1L (0xFFFF_F1DA) TBARG1L (0xFFFF_F1EA) TBBRG1L (0xFFFF_F1FA) TB8RG1H (0xFFFF_F1CB) TB9RG1H (0xFFFF_F1DB) TBARG1H (0xFFFF_F1EB) TBBRG1H (0xFFFF_F1FB) TB8CP0L (0xFFFF_F1CC) TB9CP0L (0xFFFF_F1DC) TB9CP1L (0xFFFF_F1DE) TBACP0L (0xFFFF_F1EC) TBBCP0L (0xFFFF_F1FC) TBACP1L (0xFFFF_F1EE) TBBCPIL (0xFFFF_F1FE) Capture registers TB8CP0H (0xFFFF_F1CD) TB9CP0H (0xFFFF_F1DD) TBACP0H (0xFFFF_F1ED) TBBCP0H (0xFFFF_F1FD) TB8CP1L (0xFFFF_F1CE) TB8CP1H (0xFFFF_F1CF) TB9CP1H (0xFFFF_F1DF) TBACP1H (0xFFFF_F1EF) TBBCPIH (0xFFFF_F1FF) TMP1942CY/CZ-191 TX1942CY/CZ Table 3.10.4 Specification Differences Among the TMRB Channels Specification External clock/ capture trigger input pins Capture trigger timer Timer flip-flop output pin Timer run register Timer mode register Timer flip-flop control register TBCRG0L (0xFFFF_F208) TBDRG0L (0xFFFF_F218) TBDRG1L (0xFFFF_F21A) TBCRUN (0xFFFF_F200) TBCMOD (0xFFFF_F202) TBDRUN (0xFFFF_F210) TBDMOD (0xFFFF_F212) TA5OUT TA5OUT Channel TMRBC TMRBD External pins Register name Timer registers (address) TBCRG0H (0xFFFF_F209) TBDRG0H (0xFFFF_F219) TBCRG1L (0xFFFF_F20A) TBCRG1H (0xFFFF_F20B) TBDRG1H (0xFFFF_F21B) TBCCP0L (0xFFFF_F20C) TBDCP0L (0xFFFF_F21C) TBDCP1L (0xFFFF_F21E) TBDCP1H (0xFFFF_F21F) Capture registers TBCCP0H (0xFFFF_F20D) TBDCP0H (0xFFFF_F21D) TBCCP1L (0xFFFF_F20E) TBCCP1H (0xFFFF_F20F) TMP1942CY/CZ-192 3.10.1 Internal Data Bus Internal Data Bus Block Diagrams Prescaler Clock Source: T0 2 T2 Capture Register 0 TB0CP0H/L TB0MOD run/ clear TB0RUN TA3OUT TB0IN0 TB0IN1 Capture & External Control Selector TB0MOD T0 (From TMRA23) Timer Flip Flop Control Timer Flip Flop TB0FF0 Timer Flip Flop Output TB0OUT TMRB0 Interrupt INTTB0 Figure 3.10.1 TMRB0/1 and TMRB to TMRBD Block Diagram Match Detect TMP1942CY/CZ-193 16-bit Comparator (CP0) Match Detect 16-bit Timer Register TB0RG0H/L TB0RUN Over-Flow IInterrupt Output Register 1 Interrupt Output Register 0 Interrupt Output 16-bit Comparator (CP1) 16-bit Timer Register TB0RG1H/L 16-bit Timer Status Register TB0ST TX1942CY/CZ Internal Data Bus Internal Data Bus run/ clear 2 T2 TB2MOD Internal Data Bus Prescaler Clock Source: T0 TA3OUT (From TMRA23) TB2IN0 TB2IN1 Capture & External Interrupt TB2RUN Selector Count Timer Flip Flop Control Output TB2OUT Figure 3.10.2 TMRB2/3 Block Diagram TMRB2 Interrupt INTTB2 TMP1942CY/CZ-194 16-bit Comperator (CP0) 16-bit Timer Register TB2RG0H/L Match Detect TB2RUN Up-Down Interrupt Output Over Flow Interrupt Output Register 0 Interrupt Output Register 1 Interrupt Output Under Flow Interrupt Output Match Detect 16-bit Comparator (CP1) 16-bit Timer Register TB2RG1H/L Internal Data Bus TX1942CY/CZ 16-bit Timer Status Register TB2ST TX1942CY/CZ 3.10.2 Function description of each circuit (1) Prescaler The TMP1942 has a 5-bit prescaler to supply a clock to TMRB0. The prescaler's input clock T0 has a frequency of fperiph, fperiph/2, or fperiph/4 as selected by SYSCR0 @fc = 32 MHz Peripheral Clock Selection |